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Volumn 70, Issue , 2012, Pages 67-72

An analysis on the ambipolar current in Si double-gate tunnel FETs

Author keywords

Ambipolar current; Scaling; TFET; Top and bottom contacts; Tunnel FET

Indexed keywords

AMBIPOLAR; BOTTOM CONTACTS; DESIGN PARAMETERS; DOUBLE-GATE; FIELD DISTRIBUTION; GATE VOLTAGES; NUMERICAL DEVICE SIMULATION; SCALING; TFET; TUNNEL FET; TUNNEL FIELD EFFECT TRANSISTOR;

EID: 84858070770     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2011.11.009     Document Type: Conference Paper
Times cited : (193)

References (30)
  • 1
    • 3643062973 scopus 로고
    • Silicon surface tunnel transistor
    • W.M. Reddick, and G.A.J. Amaratunga Silicon surface tunnel transistor Appl Phys Lett 67 4 1995 494 496
    • (1995) Appl Phys Lett , vol.67 , Issue.4 , pp. 494-496
    • Reddick, W.M.1    Amaratunga, G.A.J.2
  • 2
    • 19744366972 scopus 로고    scopus 로고
    • Band-to-band tunneling in carbon nanotube field-effect transistors
    • J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris Band-to-band tunneling in carbon nanotube field-effect transistors Phys Rev Lett 93 19 2004 196805 196811
    • (2004) Phys Rev Lett , vol.93 , Issue.19 , pp. 196805-196811
    • Appenzeller, J.1    Lin, Y.-M.2    Knoch, J.3    Avouris, P.4
  • 3
    • 34547850370 scopus 로고    scopus 로고
    • Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec
    • DOI 10.1109/LED.2007.901273
    • W.Y. Choi, B.-G. Park, J.D. Lee, and T.-J.K. Liu Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec IEEE Electron Dev Lett 28 8 2007 743 745 (Pubitemid 47243563)
    • (2007) IEEE Electron Device Letters , vol.28 , Issue.8 , pp. 743-745
    • Choi, W.Y.1    Park, B.-G.2    Lee, J.D.3    Liu, T.-J.K.4
  • 4
    • 79953058995 scopus 로고    scopus 로고
    • Vertical Si-nanowire n-type tunneling FETs with low subthreshold swing (≤50 mV/decade) at room temperature
    • R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee Vertical Si-nanowire n-type tunneling FETs with low subthreshold swing (≤50 mV/decade) at room temperature IEEE Electron Dev Lett 32 2011 437 439
    • (2011) IEEE Electron Dev Lett , vol.32 , pp. 437-439
    • Gandhi, R.1    Chen, Z.2    Singh, N.3    Banerjee, K.4    Lee, S.5
  • 5
    • 64549108830 scopus 로고    scopus 로고
    • Double-gate strained-Ge heterostructure. Tunneling FET (TFET) with record high drive currents and <60 mV/dec subthreshold slope
    • Krishnamohan T, Kim D, Raghunathan S, Saraswat K. Double-gate strained-Ge heterostructure. Tunneling FET (TFET) with record high drive currents and <60 mV/dec subthreshold slope. In: IEEE tech dig - int electron devices meet; 2008.p. 947.
    • (2008) IEEE Tech Dig - Int Electron Devices Meet , pp. 947
    • Krishnamohan, T.1    Kim, D.2    Raghunathan, S.3    Saraswat, K.4
  • 7
    • 34447321846 scopus 로고    scopus 로고
    • Double-gate tunnel FET with high-κ gate dielectric
    • DOI 10.1109/TED.2007.899389
    • K. Boucart, and A.M. Ionescu Double-gate tunnel fet with high-κ gate dielectric IEEE Trans Electron Dev 54 2007 1725 1733 (Pubitemid 47061885)
    • (2007) IEEE Transactions on Electron Devices , vol.54 , Issue.7 , pp. 1725-1733
    • Boucart, K.1    Ionescu, A.M.2
  • 8
    • 67649306595 scopus 로고    scopus 로고
    • Lateral strain profile as key technology booster for all-Silicon tunnel FETs
    • K. Boucart, W. Riess, and A.M. Ionescu Lateral strain profile as key technology booster for all-Silicon tunnel FETs IEEE Electron Dev Lett 30 2009 656 658
    • (2009) IEEE Electron Dev Lett , vol.30 , pp. 656-658
    • Boucart, K.1    Riess, W.2    Ionescu, A.M.3
  • 9
    • 67650671799 scopus 로고    scopus 로고
    • Fringing-induced drain current improvement in the tunnel field-effect transistor with high-κ gate dielectrics
    • M. Schlosser, K.K. Bhuwalka, M. Sauter, T. Zilbauer, T. Sulima, and I. Eisele Fringing-induced drain current improvement in the tunnel field-effect transistor with high-κ gate dielectrics IEEE Trans Electron Devi 56 2009 100 108
    • (2009) IEEE Trans Electron Devi , vol.56 , pp. 100-108
    • Schlosser, M.1    Bhuwalka, K.K.2    Sauter, M.3    Zilbauer, T.4    Sulima, T.5    Eisele, I.6
  • 10
    • 62749117201 scopus 로고    scopus 로고
    • Performance comparison between p-i-n tunneling transistors and conventional MOSFETs
    • S.O. Koswatta, M.S. Lundstrom, and D.E. Nikonov Performance comparison between p-i-n tunneling transistors and conventional MOSFETs IEEE Trans Electron Dev 56 2007 456 465
    • (2007) IEEE Trans Electron Dev , vol.56 , pp. 456-465
    • Koswatta, S.O.1    Lundstrom, M.S.2    Nikonov, D.E.3
  • 11
    • 37149019859 scopus 로고    scopus 로고
    • Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction
    • E.-H. Toh, G.H. Wang, L. Chan, G. Samudra, and Y.-C. Yeo Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction Appl Phys Lett 91 2007 243505
    • (2007) Appl Phys Lett , vol.91 , pp. 243505
    • Toh, E.-H.1    Wang, G.H.2    Chan, L.3    Samudra, G.4    Yeo, Y.-C.5
  • 12
    • 77950306444 scopus 로고    scopus 로고
    • Tunnel field effect transistor with increased on current, low-k spacer and high-k dielectric
    • C. Anghel, P. Chilagani, A. Amara, and A. Vladimirescu Tunnel field effect transistor with increased ON current, low-k spacer and high-k dielectric Appl Phys Lett 96 2010 122104
    • (2010) Appl Phys Lett , vol.96 , pp. 122104
    • Anghel, C.1    Chilagani, P.2    Amara, A.3    Vladimirescu, A.4
  • 14
    • 34547366803 scopus 로고    scopus 로고
    • Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization
    • E.-H. Toh, G. Huiqi Wang, G. Samudra, and Y.-C. Yeo Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization Appl Phys Lett 90 2007 263507
    • (2007) Appl Phys Lett , vol.90 , pp. 263507
    • Toh, E.-H.1    Huiqi Wang, G.2    Samudra, G.3    Yeo, Y.-C.4
  • 15
    • 72049108660 scopus 로고    scopus 로고
    • On enhanced miller capacitance effect in interband tunnel transistors
    • S. Mookerjea, R. Krishnan, S. Datta, and V. Narayanan On enhanced miller capacitance effect in interband tunnel transistors IEEE Electron Dev Lett 30 10 2009 1102 1104
    • (2009) IEEE Electron Dev Lett , vol.30 , Issue.10 , pp. 1102-1104
    • Mookerjea, S.1    Krishnan, R.2    Datta, S.3    Narayanan, V.4
  • 17
    • 0036919986 scopus 로고    scopus 로고
    • Molecular electronics with carbon nanotubes
    • P. Avouris Molecular electronics with carbon nanotubes Acc Chem Res 35 2002 1026 1034
    • (2002) Acc Chem Res , vol.35 , pp. 1026-1034
    • Avouris, P.1
  • 22
    • 77956057272 scopus 로고    scopus 로고
    • Hetero-gate-dielectric tunneling field-effect transistors
    • W.Y. Choi, and W. Lee Hetero-gate-dielectric tunneling field-effect transistors IEEE Trans Electron Dev 57 2010 2317 2319
    • (2010) IEEE Trans Electron Dev , vol.57 , pp. 2317-2319
    • Choi, W.Y.1    Lee, W.2
  • 23
    • 0000821177 scopus 로고    scopus 로고
    • Method for tight-binding parametrization: Application to silicon nanostructures
    • Y.M. Niquet, C. Delerue, G. Allan, and M. Lannoo Method for tight-binding parametrization: application to silicon nanostructures Phys Rev B 62 2000 5109
    • (2000) Phys Rev B , vol.62 , pp. 5109
    • Niquet, Y.M.1    Delerue, C.2    Allan, G.3    Lannoo, M.4
  • 24
    • 18844389545 scopus 로고    scopus 로고
    • Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering
    • K.K. Bhuwalka, J. Schulze, and I. Eisele Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering IEEE Trans Electron Dev 52 2005 909
    • (2005) IEEE Trans Electron Dev , vol.52 , pp. 909
    • Bhuwalka, K.K.1    Schulze, J.2    Eisele, I.3
  • 25
    • 36249031568 scopus 로고    scopus 로고
    • Length scaling of the double gate tunnel FET with a high-k gate dielectric
    • K. Boucart, and A.M. Ionescu Length scaling of the double gate tunnel FET with a high-k gate dielectric Sol - State Electron 51 2007 1500
    • (2007) Sol - State Electron , vol.51 , pp. 1500
    • Boucart, K.1    Ionescu, A.M.2
  • 29
    • 84858079848 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors (ITRS)
    • International Technology Roadmap for Semiconductors (ITRS): < http://www.itrs.net/Links/2009ITRS/2009Chapters-2009Tables/2009-PIDS.pdf >.
  • 30
    • 80052647584 scopus 로고    scopus 로고
    • Comparison of performance, switching energy and process variations for the TFET and MOSFET in Logic
    • Avci UE, Rios R, Kuhn K, Young IA. Comparison of performance, switching energy and process variations for the TFET and MOSFET in Logic. In: Proc of VLSI symp; 2011.
    • (2011) Proc of VLSI Symp
    • Avci, U.E.1    Rios, R.2    Kuhn, K.3    Young, I.A.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.