Lateral strain profile as key technology booster for all-silicon tunnel FETs

IEEE Electron Device Letters

Volumn 30, Issue 6, 2009, Pages 656-658

  Boucart, Kathy ^a   Ionescu, Adrian Mihai ^a   Riess, Walter ^b  

^a EPFL   (Switzerland)

^b IBM RESEARCH ZURICH   (Switzerland)

Author keywords

Band to band tunneling; Bandgap engineering; Silicon nanowires; Strain engineering; Surface tunneling transistor (STT); Tunnel FET

Indexed keywords

BAND-TO-BAND TUNNELING; BANDGAP ENGINEERING; SILICON NANOWIRES; STRAIN ENGINEERING; TUNNEL FET;

ELECTRIC WIRE; ENERGY GAP; FIELD EFFECT TRANSISTORS; GATES (TRANSISTOR); LOGIC DESIGN; MOSFET DEVICES; NANOWIRES; TUNNELING (EXCAVATION); TUNNELS;

MESFET DEVICES;

EID: 67649306595     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2018127     Document Type: Article

References (13)

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