55 nm capacitor-less 1T DRAM cell transistor with non-overlap structure

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Song, Ki Whan ^c   Jeong, Hoon ^a   Lee, Jae Wook ^c   Hong, Sung In ^a   Tak, Nam Kyun ^c   Kim, Young Tae ^b   Choi, Yong Lack ^a   Joo, Han Sung ^c   Kim, Sung Hwan ^a   Song, Ho Ju ^a   Oh, Yong Chul ^a   Kim, Woo Seop ^c   Lee, Yeong Taek ^c   Oh, Kyungseok ^b   Kim, Changhyun ^c  

^a ATD   (South Korea)

^b CAE Team   (South Korea)

^c SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITOR-LESS; CELL TRANSISTORS; DEVICE STRUCTURES; DRAM CELL TRANSISTORS; GATE LENGTHS; JUNCTION LEAKAGES; NON OVERLAPS; RETENTION TIME;

CAPACITORS; DYNAMIC RANDOM ACCESS STORAGE; ELECTRON DEVICES;

CAPACITANCE;

EID: 64549147872     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796818     Document Type: Conference Paper

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