Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature

IEEE Electron Device Letters

Volumn 32, Issue 4, 2011, Pages 437-439

  Gandhi, Ramanathan ^a,b   Chen, Zhixian ^a   Singh, Navab ^a   Banerjee, Kaustav ^c   Lee, Sungjoo ^b  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c University of California   (United States)

Author keywords

CMOS technology; gate all around (GAA); subthreshold swing (SS); top down; tunneling field effect transistor (TFET); vertical silicon nanowire (NW) (SiNW)

Indexed keywords

CMOS TECHNOLOGY; GATE-ALL-AROUND; SUBTHRESHOLD SWING; TOP-DOWN; TUNNELING FIELD-EFFECT TRANSISTOR (TFET); VERTICAL SILICON NANOWIRE (NW) (SINW);

CMOS INTEGRATED CIRCUITS; DRAIN CURRENT; FIELD EFFECT TRANSISTORS; GALLIUM ALLOYS;

NANOWIRES;

EID: 79953058995     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2106757     Document Type: Article

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