Synchronous-logic and globally-asynchronous- locally-synchronous (GALS) acoustic digital signal processors

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 3, 2012, Pages 769-780

  Chong, Kwen Siong ^a   Chang, Kok Leong ^b   Gwee, Bah Hwee ^a   Chang, Joseph S ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b INSTITUTE OF MATERIALS RESEARCH AND ENGINEERING   (Singapore)

Author keywords

Asynchronous logic; Dynamic voltage scaling; GALS; Synchronous logic low power

Indexed keywords

ACOUSTIC SIGNAL DETECTION; ASYNCHRONOUS-LOGIC; CLOCK DOMAINS; CLOCK GATING TECHNIQUES; CMOS PROCESSS; DESIGN APPROACHES; DYNAMIC VOLTAGE SCALING; GALS; GLOBAL CLOCKS; IDENTICAL FUNCTIONALITIES; LIBRARY CELLS; LIFE SPAN; LOW POWER; LOW-POWER OPERATION; POWER EFFICIENCY; POWER EFFICIENT; SIGNALING PROTOCOL; SUBSEQUENT REDUCTION;

CLOCKS; CMOS INTEGRATED CIRCUITS; DESIGN; DIGITAL SIGNAL PROCESSORS; LOW POWER ELECTRONICS; SIGNAL PROCESSING; VOLTAGE STABILIZING CIRCUITS;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 84857820867     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2181678     Document Type: Article

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