Ultralow-power operation in subthreshold regimes applying clockless logic

Proceedings of the IEEE

Volumn 98, Issue 2, 2010, Pages 299-314

  Jorgenson, Ryan D ^a   Sorensen, Lief ^a   Leet, Dan ^a   Hagedorn, Michael S ^a   Lamb, David R ^a   Friddell, Thomas Hal ^b   Snapp, Warren P ^b  

^a Camgian Microsystems   (United States)

^b BOEING COMPANY   (United States)

Author keywords

Asynchronous logic circuits; Circuit modeling; Circuit reliability; Circuit simulation; Circuits; CMOS digital integrated circuits; CMOS integrated circuits; Combinational logic circuits; Digital circuits; Ultralarge scale integration

Indexed keywords

CIRCUIT SIMULATION; CLOCKS; CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ENERGY CONSERVATION; INTEGRATED CIRCUIT MANUFACTURE; LOGIC CIRCUITS; LOW POWER ELECTRONICS; NETWORKS (CIRCUITS); THRESHOLD ELEMENTS;

ASYNCHRONOUS LOGIC CIRCUITS; CIRCUIT MODELING; CIRCUIT RELIABILITY; CMOS DIGITAL INTEGRATED CIRCUITS; COMBINATIONAL LOGIC CIRCUITS; ULTRALARGE SCALE INTEGRATION;

COMPUTER CIRCUITS;

EID: 75649131497     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2009.2035449     Document Type: Article

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