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Volumn 43, Issue 3, 2008, Pages 695-705

AsAP: An asynchronous array of simple processors

Author keywords

Array processor; Chip multi processor; Digital signal processing; DSP; GALS; Globally asynchronous locally synchronous; Many core; MIMD; Multi core

Indexed keywords

CMOS INTEGRATED CIRCUITS; IMAGE CODING; IMAGE COMPRESSION; WIRELESS LOCAL AREA NETWORKS (WLAN);

EID: 40149087224     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.916616     Document Type: Article
Times cited : (63)

References (33)
  • 1
    • 4143066042 scopus 로고    scopus 로고
    • A parallel programmable energy-efficient architecture for computationally-intensive DSP systems
    • Nov
    • B. M. Baas, "A parallel programmable energy-efficient architecture for computationally-intensive DSP systems," in 37th Asilomar Conf. Signals, Systems and Computers, Nov. 2003.
    • (2003) 37th Asilomar Conf. Signals, Systems and Computers
    • Baas, B.M.1
  • 2
    • 0003657403 scopus 로고
    • Globally-asynchronous locally-synchronous systems,
    • Ph.D. dissertation, Stanford Univ, Stanford, CA, Oct
    • D. M. Chapiro, "Globally-asynchronous locally-synchronous systems," Ph.D. dissertation, Stanford Univ., Stanford, CA, Oct. 1984.
    • (1984)
    • Chapiro, D.M.1
  • 5
    • 2442653861 scopus 로고    scopus 로고
    • How scaling will change processor architecture
    • M. Horowitz and W. Dally, "How scaling will change processor architecture," in IEEE ISSCC Dig. Tech. Papers. 2004, pp. 132-133.
    • (2004) IEEE ISSCC Dig. Tech. Papers , pp. 132-133
    • Horowitz, M.1    Dally, W.2
  • 10
    • 33646922057 scopus 로고    scopus 로고
    • The future of wires
    • Apr
    • R. Ho, K. W. Mai, and M. A. Horowitz, "The future of wires," Proc. IEEE, vol. 89, no. 4, pp. 490-504, Apr. 2001.
    • (2001) Proc. IEEE , vol.89 , Issue.4 , pp. 490-504
    • Ho, R.1    Mai, K.W.2    Horowitz, M.A.3
  • 11
    • 0022092257 scopus 로고
    • VLSI array processors
    • Jul
    • S. Y. Kung, "VLSI array processors," IEEE ASSP Mag., vol. 2, no. 3, pp. 4-22, Jul. 1985.
    • (1985) IEEE ASSP Mag , vol.2 , Issue.3 , pp. 4-22
    • Kung, S.Y.1
  • 14
    • 0034848112 scopus 로고    scopus 로고
    • Route packets, not wires: On-chip interconnection networks
    • Jun
    • W. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," in IEEE Int. Conf Design Automation, Jun. 2001, pp. 684-689.
    • (2001) IEEE Int. Conf Design Automation , pp. 684-689
    • Dally, W.1    Towles, B.2
  • 16
    • 2442446545 scopus 로고    scopus 로고
    • A digitally controlled PLL for SOC applications
    • May
    • T. Olsson and P. Nilsson, "A digitally controlled PLL for SOC applications," IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 751-760, May 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.5 , pp. 751-760
    • Olsson, T.1    Nilsson, P.2
  • 21
    • 40149087896 scopus 로고    scopus 로고
    • Wireless LAN medium access control (MAC) and physical layer (PHY) specifications: High speed physical layer in the 5 GHz band, Standard for Information Technology, LAN/MAN Standard Committee of the IEEE Computer Society, New York, NY, 1999.
    • "Wireless LAN medium access control (MAC) and physical layer (PHY) specifications: High speed physical layer in the 5 GHz band," Standard for Information Technology, LAN/MAN Standard Committee of the IEEE Computer Society, New York, NY, 1999.
  • 22
    • 0036296191 scopus 로고    scopus 로고
    • Cascade-configurable and scalable DSP environment
    • T. Lin and C. Jen, "Cascade-configurable and scalable DSP environment," in Proc. IEEE ISCAS, 2002, pp. 26-29.
    • (2002) Proc. IEEE ISCAS , pp. 26-29
    • Lin, T.1    Jen, C.2
  • 23
    • 84948978169 scopus 로고    scopus 로고
    • Vector versus superscalar and VLIW architectures for embedded multimedia benchmarks
    • Nov
    • C. Kozyrakis and D. Patterson, "Vector versus superscalar and VLIW architectures for embedded multimedia benchmarks," in Proc. IEEE/ACM MICRO, Nov. 2002, pp. 283-289.
    • (2002) Proc. IEEE/ACM MICRO , pp. 283-289
    • Kozyrakis, C.1    Patterson, D.2
  • 24
    • 17044404691 scopus 로고    scopus 로고
    • A full-rate software implementation of an IEEE 802.11 a compliant digital baseband transmitter
    • Oct
    • M. Meeuwsen, O. Sattari, and B. Baas, "A full-rate software implementation of an IEEE 802.11 a compliant digital baseband transmitter," in Proc. IEEE Workshop on Signal Processing Systems, Oct. 2004, pp. 297-301.
    • (2004) Proc. IEEE Workshop on Signal Processing Systems , pp. 297-301
    • Meeuwsen, M.1    Sattari, O.2    Baas, B.3
  • 25
    • 0036279137 scopus 로고    scopus 로고
    • Development of an OFDM based high speed wireless LAN platform using the TI C6x DSP
    • Apr
    • M. F. Tariq, Y. Baltaci, T. Horseman, M. Butler, and A. Nix, "Development of an OFDM based high speed wireless LAN platform using the TI C6x DSP," in IEEE Int. Conf. Communications, Apr. 2002, pp. 522-526.
    • (2002) IEEE Int. Conf. Communications , pp. 522-526
    • Tariq, M.F.1    Baltaci, Y.2    Horseman, T.3    Butler, M.4    Nix, A.5
  • 26
    • 0034314477 scopus 로고    scopus 로고
    • A 1-V heterogeneous reconfigurable DSPIC for wireless baseband digital signal processing
    • Nov
    • H. Zhang, V. Prabhu, V. George, M. Wan, M. Benes, A. Abnous, and J. M. Rabaey, "A 1-V heterogeneous reconfigurable DSPIC for wireless baseband digital signal processing," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1697-1704, Nov. 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , Issue.11 , pp. 1697-1704
    • Zhang, H.1    Prabhu, V.2    George, V.3    Wan, M.4    Benes, M.5    Abnous, A.6    Rabaey, J.M.7
  • 30
    • 34548814965 scopus 로고    scopus 로고
    • A telecom baseband circuit based on an asynchronous network-on-chip
    • D. Lattard, E. Beigne, and C. Bernard et al., "A telecom baseband circuit based on an asynchronous network-on-chip," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 258-259.
    • (2007) IEEE ISSCC Dig. Tech. Papers , pp. 258-259
    • Lattard, D.1    Beigne, E.2    Bernard, C.3
  • 31
    • 34548858682 scopus 로고    scopus 로고
    • An 80-tile 1.28 TFLOPS network-on-chip in 65 nm CMOS
    • S. Vangal, J. Howard, and G. Ruhl et al., "An 80-tile 1.28 TFLOPS network-on-chip in 65 nm CMOS," in IEEE ISSCC Dig. Tech. Papers. 2007, pp. 98-99.
    • (2007) IEEE ISSCC Dig. Tech. Papers , pp. 98-99
    • Vangal, S.1    Howard, J.2    Ruhl, G.3
  • 32
    • 0025536878 scopus 로고
    • Transputers-past, present and future
    • Dec
    • C. Whitby-Strevens, "Transputers-past, present and future," IEEE Micro, vol. 10, no. 6, pp. 16-19, Dec. 1990.
    • (1990) IEEE Micro , vol.10 , Issue.6 , pp. 16-19
    • Whitby-Strevens, C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.