-
1
-
-
4143066042
-
A parallel programmable energy-efficient architecture for computationally-intensive DSP systems
-
Nov
-
B. M. Baas, "A parallel programmable energy-efficient architecture for computationally-intensive DSP systems," in 37th Asilomar Conf. Signals, Systems and Computers, Nov. 2003.
-
(2003)
37th Asilomar Conf. Signals, Systems and Computers
-
-
Baas, B.M.1
-
2
-
-
0003657403
-
Globally-asynchronous locally-synchronous systems,
-
Ph.D. dissertation, Stanford Univ, Stanford, CA, Oct
-
D. M. Chapiro, "Globally-asynchronous locally-synchronous systems," Ph.D. dissertation, Stanford Univ., Stanford, CA, Oct. 1984.
-
(1984)
-
-
Chapiro, D.M.1
-
3
-
-
34250863881
-
An asynchronous array of simple processors for DSP applications
-
Z. Yu, M. Meeuwsen, R. Apperson, O. Sattari, M. Lai, J. Webb, E. Work, T. Mohsenin, M. Singh, and B. Baas, "An asynchronous array of simple processors for DSP applications," in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 428-429.
-
(2006)
IEEE ISSCC Dig. Tech. Papers
, pp. 428-429
-
-
Yu, Z.1
Meeuwsen, M.2
Apperson, R.3
Sattari, O.4
Lai, M.5
Webb, J.6
Work, E.7
Mohsenin, T.8
Singh, M.9
Baas, B.10
-
5
-
-
2442653861
-
How scaling will change processor architecture
-
M. Horowitz and W. Dally, "How scaling will change processor architecture," in IEEE ISSCC Dig. Tech. Papers. 2004, pp. 132-133.
-
(2004)
IEEE ISSCC Dig. Tech. Papers
, pp. 132-133
-
-
Horowitz, M.1
Dally, W.2
-
6
-
-
0036858553
-
A 600-MHz VLIW DSP
-
Nov
-
S. Agarwala, M. D. Ales, R. Damodaran, P. Wiley, S. Mullinnix, J. Leach, A. Lell, M. Gill, A. Rajagopal, A. Chachad, M. Agarwala, J. Apostol, M. Krishnan, D. Bui, Q. An, N. S. Nagaraj, T. Wolf, and T. T. Elappuparackal, "A 600-MHz VLIW DSP," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1532-1544, Nov. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.11
, pp. 1532-1544
-
-
Agarwala, S.1
Ales, M.D.2
Damodaran, R.3
Wiley, P.4
Mullinnix, S.5
Leach, J.6
Lell, A.7
Gill, M.8
Rajagopal, A.9
Chachad, A.10
Agarwala, M.11
Apostol, J.12
Krishnan, M.13
Bui, D.14
An, Q.15
Nagaraj, N.S.16
Wolf, T.17
Elappuparackal, T.T.18
-
7
-
-
27644501870
-
Implementation of a 4th-generation 1.8 GHz dual-core SPARC v9 microprocessor
-
J. Hart, S. Choe, L. Cheng, C. Chou, A. Dixit, K. Ho, J. Hsu, K. Lee, and J. Wu, "Implementation of a 4th-generation 1.8 GHz dual-core SPARC v9 microprocessor," in IEEE ISSCC Dig. Tech. Papers. 2005, pp. 186-187.
-
(2005)
IEEE ISSCC Dig. Tech. Papers
, pp. 186-187
-
-
Hart, J.1
Choe, S.2
Cheng, L.3
Chou, C.4
Dixit, A.5
Ho, K.6
Hsu, J.7
Lee, K.8
Wu, J.9
-
8
-
-
28144464504
-
Creating the Bluegene/L supercomputer from low-power SoC AISCs
-
A. Bright, M. Ellavsky, A. Gara, R. Haring, G. Kopcsay, R. Lembach, J. Marcella, M. Ohmacht, and V. Salapura, "Creating the Bluegene/L supercomputer from low-power SoC AISCs," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 188-189.
-
(2005)
IEEE ISSCC Dig. Tech. Papers
, pp. 188-189
-
-
Bright, A.1
Ellavsky, M.2
Gara, A.3
Haring, R.4
Kopcsay, G.5
Lembach, R.6
Marcella, J.7
Ohmacht, M.8
Salapura, V.9
-
9
-
-
0345272496
-
Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling
-
G. Semeraro, G. Magklis, R. Balasubramonian, D. H. Albonesi, S. Dwarkadas, and M. L. Scott, "Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling," in Proc. Int. Symp. High-Performance Computer Architecture, 2002, pp. 29-40.
-
(2002)
Proc. Int. Symp. High-Performance Computer Architecture
, pp. 29-40
-
-
Semeraro, G.1
Magklis, G.2
Balasubramonian, R.3
Albonesi, D.H.4
Dwarkadas, S.5
Scott, M.L.6
-
10
-
-
33646922057
-
The future of wires
-
Apr
-
R. Ho, K. W. Mai, and M. A. Horowitz, "The future of wires," Proc. IEEE, vol. 89, no. 4, pp. 490-504, Apr. 2001.
-
(2001)
Proc. IEEE
, vol.89
, Issue.4
, pp. 490-504
-
-
Ho, R.1
Mai, K.W.2
Horowitz, M.A.3
-
11
-
-
0022092257
-
VLSI array processors
-
Jul
-
S. Y. Kung, "VLSI array processors," IEEE ASSP Mag., vol. 2, no. 3, pp. 4-22, Jul. 1985.
-
(1985)
IEEE ASSP Mag
, vol.2
, Issue.3
, pp. 4-22
-
-
Kung, S.Y.1
-
12
-
-
0037969181
-
A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network
-
M. B. Taylor, J. Kim, J. Miller, D. Wentzlaff, F. Ghodrat, B. Greenwald, H. Hoffman, P. Johnson, W. Lee, A. Saraf, N. Shnidman, V. Stumpen, S. Amarasinghe, and A. Agarwal, "A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 170-171.
-
(2003)
IEEE ISSCC Dig. Tech. Papers
, pp. 170-171
-
-
Taylor, M.B.1
Kim, J.2
Miller, J.3
Wentzlaff, D.4
Ghodrat, F.5
Greenwald, B.6
Hoffman, H.7
Johnson, P.8
Lee, W.9
Saraf, A.10
Shnidman, N.11
Stumpen, V.12
Amarasinghe, S.13
Agarwal, A.14
-
13
-
-
0037969184
-
A wire-delay scalable microprocessor architecture for high performance systems
-
S. W. Keckler, D. Burger, C. R. Moore, R. Nagarajan, K. Sankaralingam, V. Agarwal, M. S. Hrishikesh, N. Ranganathan, and P. Shivakumar, "A wire-delay scalable microprocessor architecture for high performance systems," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 168-169.
-
(2003)
IEEE ISSCC Dig. Tech. Papers
, pp. 168-169
-
-
Keckler, S.W.1
Burger, D.2
Moore, C.R.3
Nagarajan, R.4
Sankaralingam, K.5
Agarwal, V.6
Hrishikesh, M.S.7
Ranganathan, N.8
Shivakumar, P.9
-
14
-
-
0034848112
-
Route packets, not wires: On-chip interconnection networks
-
Jun
-
W. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," in IEEE Int. Conf Design Automation, Jun. 2001, pp. 684-689.
-
(2001)
IEEE Int. Conf Design Automation
, pp. 684-689
-
-
Dally, W.1
Towles, B.2
-
15
-
-
4644295630
-
Evaluating the Imagine stream architecture
-
Jun
-
J. H. Ahn, W. J. Dally, B. Khailany, U. J. Kapasi, and A. Das, "Evaluating the Imagine stream architecture." in Proc. Int. Symp. Computer Architecture, Jun. 2004, pp. 19-23.
-
(2004)
Proc. Int. Symp. Computer Architecture
, pp. 19-23
-
-
Ahn, J.H.1
Dally, W.J.2
Khailany, B.3
Kapasi, U.J.4
Das, A.5
-
16
-
-
2442446545
-
A digitally controlled PLL for SOC applications
-
May
-
T. Olsson and P. Nilsson, "A digitally controlled PLL for SOC applications," IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 751-760, May 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, Issue.5
, pp. 751-760
-
-
Olsson, T.1
Nilsson, P.2
-
17
-
-
34648839900
-
A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains
-
Oct
-
R. W. Apperson, Z. Yu, M. J. Meeuwsen, T. Mohsenin, and B. M. Baas, "A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 10, pp. 1125-1134, Oct. 2007.
-
(2007)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.15
, Issue.10
, pp. 1125-1134
-
-
Apperson, R.W.1
Yu, Z.2
Meeuwsen, M.J.3
Mohsenin, T.4
Baas, B.M.5
-
18
-
-
0034430971
-
A 4-way VLIW embedded multimedia processor
-
A. Suga, T. Sukemura, H. Wada, H. Miyake, Y. Nakamura, Y. Takebe, K. Azegami, Y. Himura, H. Okano, T. Shiota, M. Saito, S. Wakayama, T. Ozawa, T. Satoh, A. Sakutai, T. Katayama, K. Abe, and K. Kuwano, "A 4-way VLIW embedded multimedia processor," in IEEE ISSCC Dig. Tech. Papers. 2000, pp. 240-241.
-
(2000)
IEEE ISSCC Dig. Tech. Papers
, pp. 240-241
-
-
Suga, A.1
Sukemura, T.2
Wada, H.3
Miyake, H.4
Nakamura, Y.5
Takebe, Y.6
Azegami, K.7
Himura, Y.8
Okano, H.9
Shiota, T.10
Saito, M.11
Wakayama, S.12
Ozawa, T.13
Satoh, T.14
Sakutai, A.15
Katayama, T.16
Abe, K.17
Kuwano, K.18
-
19
-
-
27344435504
-
The design and implementation of a first-generation CELL processor
-
D. Pham, S. Asano, M. Bolliger, M. N. Day, H. P. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi, M. Riley, D. Shippy, D. Stasiak, M. Suzuoki, M. Wang, J. Warnock, S. Weitzel, D. Wendel, T. Yamazaki, and K. Yazawa, "The design and implementation of a first-generation CELL processor," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 184-185.
-
(2005)
IEEE ISSCC Dig. Tech. Papers
, pp. 184-185
-
-
Pham, D.1
Asano, S.2
Bolliger, M.3
Day, M.N.4
Hofstee, H.P.5
Johns, C.6
Kahle, J.7
Kameyama, A.8
Keaty, J.9
Masubuchi, Y.10
Riley, M.11
Shippy, D.12
Stasiak, D.13
Suzuoki, M.14
Wang, M.15
Warnock, J.16
Weitzel, S.17
Wendel, D.18
Yamazaki, T.19
Yazawa, K.20
more..
-
21
-
-
40149087896
-
-
Wireless LAN medium access control (MAC) and physical layer (PHY) specifications: High speed physical layer in the 5 GHz band, Standard for Information Technology, LAN/MAN Standard Committee of the IEEE Computer Society, New York, NY, 1999.
-
"Wireless LAN medium access control (MAC) and physical layer (PHY) specifications: High speed physical layer in the 5 GHz band," Standard for Information Technology, LAN/MAN Standard Committee of the IEEE Computer Society, New York, NY, 1999.
-
-
-
-
22
-
-
0036296191
-
Cascade-configurable and scalable DSP environment
-
T. Lin and C. Jen, "Cascade-configurable and scalable DSP environment," in Proc. IEEE ISCAS, 2002, pp. 26-29.
-
(2002)
Proc. IEEE ISCAS
, pp. 26-29
-
-
Lin, T.1
Jen, C.2
-
23
-
-
84948978169
-
Vector versus superscalar and VLIW architectures for embedded multimedia benchmarks
-
Nov
-
C. Kozyrakis and D. Patterson, "Vector versus superscalar and VLIW architectures for embedded multimedia benchmarks," in Proc. IEEE/ACM MICRO, Nov. 2002, pp. 283-289.
-
(2002)
Proc. IEEE/ACM MICRO
, pp. 283-289
-
-
Kozyrakis, C.1
Patterson, D.2
-
24
-
-
17044404691
-
A full-rate software implementation of an IEEE 802.11 a compliant digital baseband transmitter
-
Oct
-
M. Meeuwsen, O. Sattari, and B. Baas, "A full-rate software implementation of an IEEE 802.11 a compliant digital baseband transmitter," in Proc. IEEE Workshop on Signal Processing Systems, Oct. 2004, pp. 297-301.
-
(2004)
Proc. IEEE Workshop on Signal Processing Systems
, pp. 297-301
-
-
Meeuwsen, M.1
Sattari, O.2
Baas, B.3
-
25
-
-
0036279137
-
Development of an OFDM based high speed wireless LAN platform using the TI C6x DSP
-
Apr
-
M. F. Tariq, Y. Baltaci, T. Horseman, M. Butler, and A. Nix, "Development of an OFDM based high speed wireless LAN platform using the TI C6x DSP," in IEEE Int. Conf. Communications, Apr. 2002, pp. 522-526.
-
(2002)
IEEE Int. Conf. Communications
, pp. 522-526
-
-
Tariq, M.F.1
Baltaci, Y.2
Horseman, T.3
Butler, M.4
Nix, A.5
-
26
-
-
0034314477
-
A 1-V heterogeneous reconfigurable DSPIC for wireless baseband digital signal processing
-
Nov
-
H. Zhang, V. Prabhu, V. George, M. Wan, M. Benes, A. Abnous, and J. M. Rabaey, "A 1-V heterogeneous reconfigurable DSPIC for wireless baseband digital signal processing," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1697-1704, Nov. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.11
, pp. 1697-1704
-
-
Zhang, H.1
Prabhu, V.2
George, V.3
Wan, M.4
Benes, M.5
Abnous, A.6
Rabaey, J.M.7
-
27
-
-
0036045954
-
PipeRench: A virtualized programmable datapath in 0.18 micron technology
-
H. Schmit, D. Whelihan, A. Tsai, M. Moe, B. Levine, and R. R. Taylor, "PipeRench: A virtualized programmable datapath in 0.18 micron technology," in Proc. IEEE Custom Integrated Circuits Conf., 2002, pp. 63-66.
-
(2002)
Proc. IEEE Custom Integrated Circuits Conf
, pp. 63-66
-
-
Schmit, H.1
Whelihan, D.2
Tsai, A.3
Moe, M.4
Levine, B.5
Taylor, R.R.6
-
28
-
-
0033688597
-
Smart memories: A modular reconfigurable architecture
-
Jun
-
K. Mai, T. Paaske, and N. Jayasena et al., "Smart memories: A modular reconfigurable architecture," in Proc. Int. Symp. Computer Architecture, Jun. 2000, pp. 161-171.
-
(2000)
Proc. Int. Symp. Computer Architecture
, pp. 161-171
-
-
Mai, K.1
Paaske, T.2
Jayasena, N.3
-
29
-
-
4644316767
-
Synchroscalar: A multiple clock domain, power-aware, tile-based embedded processor
-
Jun
-
J. Oliver, R. Rao, P. Sultana, J. Crandall, E. Czernikowski, L. W. Jones, D. Franklin, V. Akella, and F. T. Chong, "Synchroscalar: A multiple clock domain, power-aware, tile-based embedded processor," in Proc. Int. Symp. Computer Architecture. Jun. 2004.
-
(2004)
Proc. Int. Symp. Computer Architecture
-
-
Oliver, J.1
Rao, R.2
Sultana, P.3
Crandall, J.4
Czernikowski, E.5
Jones, L.W.6
Franklin, D.7
Akella, V.8
Chong, F.T.9
-
30
-
-
34548814965
-
A telecom baseband circuit based on an asynchronous network-on-chip
-
D. Lattard, E. Beigne, and C. Bernard et al., "A telecom baseband circuit based on an asynchronous network-on-chip," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 258-259.
-
(2007)
IEEE ISSCC Dig. Tech. Papers
, pp. 258-259
-
-
Lattard, D.1
Beigne, E.2
Bernard, C.3
-
32
-
-
0025536878
-
Transputers-past, present and future
-
Dec
-
C. Whitby-Strevens, "Transputers-past, present and future," IEEE Micro, vol. 10, no. 6, pp. 16-19, Dec. 1990.
-
(1990)
IEEE Micro
, vol.10
, Issue.6
, pp. 16-19
-
-
Whitby-Strevens, C.1
|