High performance asynchronous design using single-track full-buffer standard cells

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 6, 2006, Pages 1444-1454

  Ferretti, Marcos ^a,b,c   Beerel, Peter A ^a,b,d  

^a IEEE   (Brazil)

^b University of Southern California   (United States)

^c PST Industria Eletronica da Amazonia Ltda   (Brazil)

^d Fulcrum Microsystems Inc   (United States)

Author keywords

64 bit prefix adder; Asynchronous logic circuits; High speed standard cell design; Pipeline processing; Single track template

Indexed keywords

64-BIT PREFIX ADDERS; ASYNCHRONOUS LOGIC CIRCUITS; HIGH-SPEED STANDARD CELL DESIGN; PIPELINE PROCESSING; SINGLE-TRACK TEMPLATES;

ADDERS; ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTER AIDED DESIGN; ELECTRIC BATTERIES; MICROPROCESSOR CHIPS;

LOGIC DESIGN;

EID: 33746622166     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.874308     Document Type: Article

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