Three Generations of Asynchronous Microprocessors

IEEE Design and Test of Computers

Volumn 20, Issue 6, 2003, Pages 9-17

  Martin, Alain J ^a   Nyström, Mika ^a   Wong, Catherine G ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CALTECH ASYNCHRONOUS MICROPROCESSORS (CAM); PHASE HANDSHAKING EXPANSIONS (PHE); QUASI-DELAY-INSENSITIVE (QDI) CIRCUITS;

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; DATA STORAGE EQUIPMENT; DESIGN FOR TESTABILITY; ENERGY EFFICIENCY; REDUCED INSTRUCTION SET COMPUTING; THRESHOLD VOLTAGE; TRANSISTORS; VLSI CIRCUITS; VOLTAGE CONTROL;

MICROPROCESSOR CHIPS;

EID: 0346265964     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1246159     Document Type: Article

References (10)

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8. D.P. Bhandakar, Alpha Implementations and Architectures, Digital Press, 1996.
9. T. Burd, "General Processor Information," Apr. 2000, http://tech-www.informatlk.uni-hamburg.de/lehre/ss2002/pc-technologie/docs/ microprocessor-summary.pdf.
10. H. van Gageldonk et al., "An Asynchronous Low-Power 80C51 Microcontroller," Proc. 4th Int'l Symp. Asynchronous Circuits and Systems (ASYNC 98), IEEE CS Press, 1998, pp. 96-107.