Globally asynchronous, locally synchronous circuits: Overview and outlook

IEEE Design and Test of Computers

Volumn 24, Issue 5, 2007, Pages 430-441

  Krstić, Miloš ^a   Grass, Eckhard ^a   Gürkaynal, Frank K ^b   Vivet, Pascal ^c  

^a IHP   (Germany)

^b EPFL   (Switzerland)

^c Advanced Design Dept of the French Atomic Energy Commission Lab for Elec and Info Tech   (France)

Author keywords

Asynchronous synchronous operation; Electromagnetic interference; Frequency synchronization; GALS; Interfaces; Power demand; Synchronization; System on a chip; VLSI

Indexed keywords

FREQUENCY SYNCHRONIZATION; GLOBALLY ASYNCHRONOUS, LOCALLY SYNCHRONOUS (GALS); SYSTEM-ON-A-CHIP;

INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; SIGNAL INTERFERENCE; SYNCHRONIZATION; VLSI CIRCUITS;

COMPUTER CIRCUITS;

EID: 35348857534     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2007.164     Document Type: Review

References (20)

1. R. Ginosar, "Fourteen Ways to Fool Your Synchronizer," Proc. 9th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 03), IEEE CS Press, 2003, pp. 89-96.
2. D. Chapiro, "Globally-Asynchronous Locally-Synchronous Systems," doctoral dissertation, Dept. of Computer Science, Stanford Univ., 1984.
3. K. Yun and R. Donohue, "Pausible Clocking: A First Step toward Heterogeneous Systems," Proc. IEEE Int'l Conf. Computer Design: VLSI in Computers and Processors (ICCD 96), IEEE CS Press, 1996, pp. 118-127.
4. J. Muttersbach, T. Villiger, and W. Fichtner, "Practical Design of Globally-Asynchronous Locally-Synchronous Systems," Proc. 6th Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNC 00), IEEE CS Press, 2000, pp. 52-59.
5. J. Kessels et al., "Clock Synchronization through Handshake Signalling," Proc. 8th Int'l Symp. Asynchronous Circuits and Systems (ASYNC 02), IEEE CS Press, 2002, pp. 59-68.
6. M. Krstić et al., "System Integration by Request-Driven GALS Design," IEE Proc. Computers & Digital Techniques, vol. 153, no. 5, Sept. 2006, pp. 362-372.
7. R. Mullins and S. Moore, "Demystifying Data-Driven and Pausible Clocking Schemes," Proc. 13th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 07), IEEE CS Press, 2007, pp. 175-185.
8. T. Chelcea and S. Nowick, "Low-Latency Asynchronous FIFO's Using Token Rings," Proc. 6th Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNC 00), IEEE CS Press, 2000, pp. 210-220.
9. A. Chakraborty and M. Greenstreet, "Efficient Self-Timed Interfaces for Crossing Clock Domains," Proc. 9th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 03), IEEE CS Press, 2003, pp. 78-88.
10. E. Beigne and P. Vivet, "Design of On-Chip and Off-Chip Interfaces for a GALS NoC Architecture," Proc. 12th IEEE Intl Symp. Asynchronous Circuits and Systems (ASYNC 06), IEEE CS Press, 2006, pp. 172-181.
11. R. Dobkin, R. Ginosar, and C. Sotiriu, "Data Synchronization Issues in GALS SoCs," Proc. 10th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 04), IEEE CS Press, 2004, pp. 170-179.
12. T. Bjerregaard et al., "An OCP Compliant Network Adapter for GALS-Based SoC Design Using the MANGO Network-on-Chip," Proc. Int'l Symp. System-on-Chip (SoC 05), IEEE Press, 2005, pp. 171-174.
13. K. van Berkel, A. Peeters, and F. te Beest, "Adding Synchronous and LSSD Modes to Asynchronous Circuits," Proc. 8th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 02), IEEE CS Press, 2002, pp. 161-170.
14. F. Gürkaynak et al., "GALS at ETH Zurich: Success or Failure?" Proc. 12th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 06), IEEE CS Press, 2006, pp. 150-159.
15. E. Talpes and D. Marculescu, "Toward a Multiple Clock/Voltage Island Design Style for Power-Aware Processors," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 13, no. 5, May 2005, pp. 591-603.
16. F.K. Gürkaynak et al., "Improving DPA Security by Using Globally-Asynchronous Locally-Synchronous Systems," Proc. 31st European Solid-State Circuits Conf. (ESSCIRC 05), IEEE Press, 2005, pp. 407-410.
17. D. Lattard et al., "A Telecom Baseband Circuit Based on an Asynchronous Network-on-Chip," Proc. Int'l Solid-State Circuits Conf. (ISSCC 07), IEEE Press, 2007, pp. 258-601.
18. R. Dobkin et al., "An Asynchronous Router for Multiple Service Levels Networks on Chip," Proc. 11th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 05), IEEE CS Press, 2005, pp. 44-53.
19. G. DeMicheli and L. Benini, Networks on Chips: Technology and Tools (Systems on Silicon), Morgan Kaufmann, 2006.
20. Z. Yu and B.M. Baas, "Implementing Tile-Based Chip Multiprocessors with GALS Clocking Styles," Proc. IEEE Int'l Conf. Computer Design (ICCD 06), IEEE Press, 2006, pp. 174-180.