-
1
-
-
0036913332
-
A 1.1-V 270- μA mixed-signal hearing aid chip
-
Dec
-
D. G. Gata et al., "A 1.1-V 270- μA mixed-signal hearing aid chip," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1670-1678, Dec. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.12
, pp. 1670-1678
-
-
Gata, D.G.1
-
2
-
-
0034317261
-
A 660- μW 50-MOPS 1-V DSP for a hearing aid chip set
-
Nov
-
P. Mosch et al., "A 660- μW 50-MOPS 1-V DSP for a hearing aid chip set," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1705-1712, Nov. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.11
, pp. 1705-1712
-
-
Mosch, P.1
-
3
-
-
34047188489
-
A 16-channel low power non-uniform, spaced filter bank core for digital hearing aids
-
Sep
-
K.-S. Chong, B.-H. Gwee, and J. S. Chang, "A 16-channel low power non-uniform, spaced filter bank core for digital hearing aids," IEEE Trans. Circuits Syst. II, vol. 53, no. 9, pp. 853-857, Sep. 2006.
-
(2006)
IEEE Trans. Circuits Syst. II
, vol.53
, Issue.9
, pp. 853-857
-
-
Chong, K.-S.1
Gwee, B.-H.2
Chang, J.S.3
-
4
-
-
27644480487
-
A micropower low-distortion digital class-D amplifier based on an algorithmic pulsewidth modulator
-
Oct
-
B.-H. Gwee, J. S. Chang, and V. Adrian, "A micropower low-distortion digital class-D amplifier based on an algorithmic pulsewidth modulator," IEEE Trans. Circuits Syst. I, vol. 52, no. 10, pp. 2007-2022, Oct. 2005.
-
(2005)
IEEE Trans. Circuits Syst. I
, vol.52
, Issue.10
, pp. 2007-2022
-
-
Gwee, B.-H.1
Chang, J.S.2
Adrian, V.3
-
5
-
-
3042739407
-
Design optimization of low-power high-performance DSP building blocks
-
Jul
-
T. Genmeke, M. Gansen, H. J. Stockmanns, and T. G. Noll, "Design optimization of low-power high-performance DSP building blocks," IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1131-1139, Jul. 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, Issue.7
, pp. 1131-1139
-
-
Genmeke, T.1
Gansen, M.2
Stockmanns, H.J.3
Noll, T.G.4
-
6
-
-
0003850954
-
-
2nd ed. Upper Saddle River, NJ: Prentice Hall
-
J. B. Rabeay, A. Chandrakasan, and B. Nikolić, Digital Integrated Circuits: A Design Perspective, 2nd ed. Upper Saddle River, NJ: Prentice Hall, 2002.
-
(2002)
Digital Integrated Circuits: A Design Perspective
-
-
Rabeay, J.B.1
Chandrakasan, A.2
Nikolić, B.3
-
7
-
-
0036916414
-
Methods for true power minimization
-
R. W. Brodersen, M. A. Horowitz, D. Markovic, B. Nikolić, and V. Stojanovic, "Methods for true power minimization," in Proc. IEEE ICCAD, 2002, pp. 35-42.
-
(2002)
Proc. IEEE ICCAD
, pp. 35-42
-
-
Brodersen, R.W.1
Horowitz, M.A.2
Markovic, D.3
Nikolić, B.4
Stojanovic, V.5
-
9
-
-
0035247709
-
An asynchronous instruction length decoder
-
Feb
-
K. S. Stevens et al., "An asynchronous instruction length decoder," IEEE J. Solid-State Circuits, vol. 36, no. 2, pp. 217-228, Feb. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.2
, pp. 217-228
-
-
Stevens, K.S.1
-
10
-
-
0033079548
-
Designing asynchronous circuits for low power: An IFIR filter bank for a digital hearing aid
-
Feb
-
L. S. Nielsen and J. Sparsø, "Designing asynchronous circuits for low power: An IFIR filter bank for a digital hearing aid," Proc. IEEE, vol. 87, no. 2, pp. 268-281, Feb. 1999.
-
(1999)
Proc. IEEE
, vol.87
, Issue.2
, pp. 268-281
-
-
Nielsen, L.S.1
Sparsø, J.2
-
11
-
-
16544391170
-
High-throughput asynchronous datapath with software-controlled voltage scaling
-
Apr
-
Y. W. Li, G. Patounakis, K. L. Shepard, and S. M. Nowick, "High-throughput asynchronous datapath with software-controlled voltage scaling," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 704-708, Apr. 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, Issue.4
, pp. 704-708
-
-
Li, Y.W.1
Patounakis, G.2
Shepard, K.L.3
Nowick, S.M.4
-
12
-
-
0346265964
-
Three generations of asynchronous microprocessors
-
Nov.-Dec
-
A. J. Martin, M. Nyström, and C. G. Wong, "Three generations of asynchronous microprocessors," IEEE Des. Test Comput., vol. 20, no. 6, pp. 9-17, Nov.-Dec. 2003.
-
(2003)
IEEE Des. Test Comput
, vol.20
, Issue.6
, pp. 9-17
-
-
Martin, A.J.1
Nyström, M.2
Wong, C.G.3
-
13
-
-
43549103136
-
A low-energy asynchronous FFT/IFFT processor for hearing aid applications
-
K.-S. Chong, B.-H. Gwee, and J. S. Chang, "A low-energy asynchronous FFT/IFFT processor for hearing aid applications," in Proc. IEEE Int. Conf. Electron Devices and Solid-State Circuits, 2005, pp. 751-754.
-
(2005)
Proc. IEEE Int. Conf. Electron Devices and Solid-State Circuits
, pp. 751-754
-
-
Chong, K.-S.1
Gwee, B.-H.2
Chang, J.S.3
-
14
-
-
13844299623
-
A micropower low-voltage multiplier with reduced spurious switching
-
Feb
-
K.-S. Chong, B.-H. Gwee, and J. S. Chang, "A micropower low-voltage multiplier with reduced spurious switching," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 2, pp. 255-265, Feb. 2005.
-
(2005)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.13
, Issue.2
, pp. 255-265
-
-
Chong, K.-S.1
Gwee, B.-H.2
Chang, J.S.3
-
15
-
-
77957965192
-
Reconfigurable latch controllers for low power asynchronous circuits
-
M. Lewis, J. Garside, and L. Brackenbury, "Reconfigurable latch controllers for low power asynchronous circuits," in Proc. IEEE Int. Symp. Advanced Research in Asynchronous Circuits and Systems, 1999, pp. 27-35.
-
(1999)
Proc. IEEE Int. Symp. Advanced Research in Asynchronous Circuits and Systems
, pp. 27-35
-
-
Lewis, M.1
Garside, J.2
Brackenbury, L.3
-
16
-
-
0024611252
-
High-speed CMOS circuit technique
-
Feb
-
J. Yuan and C. Svensson, "High-speed CMOS circuit technique," IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 62-70, Feb. 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, Issue.1
, pp. 62-70
-
-
Yuan, J.1
Svensson, C.2
-
18
-
-
28244470100
-
A robust low voltage low energy asynchronous cany-completion sensing adder for biomedical applications
-
18-S1/2-21
-
K.-S. Chong, B.-H. Gwee, and J. S. Chang, "A robust low voltage low energy asynchronous cany-completion sensing adder for biomedical applications," in Proc. IEEE BioCAS, 2004, pp. S1/2-18-S1/2-21.
-
(2004)
Proc. IEEE BioCAS
-
-
Chong, K.-S.1
Gwee, B.-H.2
Chang, J.S.3
-
19
-
-
0037334061
-
High-speed and low-power split-radix FFT
-
Mar
-
W.-C. Yeh and C.-W. Jen, "High-speed and low-power split-radix FFT," IEEE Trans. Signal Process., vol. 51, no. 3, pp. 864-874, Mar. 2003.
-
(2003)
IEEE Trans. Signal Process
, vol.51
, Issue.3
, pp. 864-874
-
-
Yeh, W.-C.1
Jen, C.-W.2
-
20
-
-
0032677870
-
Rapid design of application specific FFT cores
-
May
-
T. J. Ding, J. V. McCanny, and Y. Hu, "Rapid design of application specific FFT cores," IEEE Trans. Signal Process., vol. 47, no. 5, pp. 1371-1381, May 1999.
-
(1999)
IEEE Trans. Signal Process
, vol.47
, Issue.5
, pp. 1371-1381
-
-
Ding, T.J.1
McCanny, J.V.2
Hu, Y.3
-
21
-
-
0033098378
-
A low-power, high-performance, 1024-point FFT processor
-
Mar
-
B. M. Bass, "A low-power, high-performance, 1024-point FFT processor," IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 380-387, Mar. 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, Issue.3
, pp. 380-387
-
-
Bass, B.M.1
-
22
-
-
11944273157
-
A 180-mV subthreshold FFT processor using a minimum energy design methodology
-
Jan
-
A. Wang and A. Chandrakasan, "A 180-mV subthreshold FFT processor using a minimum energy design methodology," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310-319, Jan. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.1
, pp. 310-319
-
-
Wang, A.1
Chandrakasan, A.2
|