A GALS infrastructure for a massively parallel multiprocessor

IEEE Design and Test of Computers

Volumn 24, Issue 5, 2007, Pages 454-463

  Plana, Luis A ^a   Furber, Steve B ^a   Temple, Steve ^a   Khan, Mukaram ^a   Shi, Yebin ^a   Wu, Jian ^a   Yang, Shufan ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

Bandwidth; Fabrics; GALS; Magnetic cores; Massively parallel multiprocessor; Neural modeling; Protocols; Receivers; Self timed interconnect; Spinnaker; Timing; Wires

Indexed keywords

BANDWIDTH; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; NEURAL NETWORKS; PACKET SWITCHING; TIMING DEVICES;

GLOBALLY ASYNCHRONOUS, LOCALLY SYNCHRONOUS (GALS); MASSIVELY PARALLEL MULTIPROCESSOR; NEURAL MODELING; PACKET-SWITCHED FABRIC; SELF-TIMED INTERCONNECT; SPINNAKER;

MULTIPROCESSING SYSTEMS;

EID: 35348906788     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2007.149     Document Type: Article

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