A highly scalable GALS crossbar using token ring arbitration

IEEE Design and Test of Computers

Volumn 24, Issue 5, 2007, Pages 464-472

  Singh, Tejpal ^a   Taubin, Alexander ^b  

^a INTEL CORPORATION   (United States)

^b Boston University   (United States)

Author keywords

Arbitration; Crossbar design; Latency; Logic gates; Protocols; Receivers; Scalability; Synchronization; Timing; Token rings

Indexed keywords

COMPUTER CIRCUITS; INTERFACES (COMPUTER); LOGIC GATES; SCALABILITY; SYNCHRONIZATION;

DISTRIBUTED ARBITRATION MECHANISM; TOKEN RINGS;

COMPUTER SYSTEMS;

EID: 35348917615     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2007.150     Document Type: Article

References (12)

1. K.A. Bowman, S.G. Duvall, and J.D. Meindl, "Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration," IEEE J. Solid-State Circuits, vol. 37, no. 2, Feb. 2002, pp. 183-190.
2. J. Muttersbach et al., "Globally-Asynchronous Locally-Synchronous Architectures to Simplify the Design of On-Chip Systems," Proc. 12th IEEE Int'l ASIC/SOC Conf., IEEE Press, 1999, pp. 317-321.
3. N. Koichi et al., "Deterministic Inter-core Synchronization with Periodically All-in-Phase Clocking for Low-Power Multi-core SoCs," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 05), IEEE Press, 2005, pp. 296-297, 599.
4. A. Chakraborty and M.R. Greenstreet, "Efficient Self-Timed Interfaces for Crossing Clock Domains," Proc. 9th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 03), IEEE CS Press, 2003, pp. 78-88.
5. T. Chelcea and S.M. Norwick, "Low Latency Asynchronous FIFO Using Token Rings," Proc. 6th Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNC 00), IEEE CS Press, 2000, pp. 210-220.
6. A. Lines, "Asynchronous Interconnect for Synchronous SoC Design," IEEE Micro, vol. 24, no. 1, Jan.-Feb. 2004, pp. 32-41.
7. A.J. Martin, Asynchronous Circuits for Token-Ring Mutual Exclusion tech. report 00000070, Computer Science Dept., California Institute of Technology, 1990.
8. A. Yakovlev et al., "Designing Asynchronous Pipeline Token Ring Interface," Proc. 2nd Working Conf. Asynchronous Design Methodologies, IEEE CS Press, 1995, pp. 32-41.
9. I. Sutherland and S. Fairbanks, "GasP: A Minimal FIFO Control," Proc. 7th Int'l Symp. Asynchronous Circuits and Systems (ASYNC 01), IEEE CS Press, 2001, pp. 46-53.
10. T. Singh and A. Taubin, "A GALS Solution Based on Highly Scalable, Low Latency, Crossbar Using Token Ring Arbitration," Proc. 49th IEEE Int'l Midwest Symp. Circuits and Systems (MWSCAS 06), IEEE Press, 2006, pp. 94-98.
11. T.-A. Chu, Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications, tech. report MIT/LCS/TR-393, MIT Laboratory for Computer Science, 1987.
12. C.L. Seitz, "System Timing," Introduction to VLSI systems, C.A. Mead and L.A. Conway, eds., Addison-Wesley, 1980, pp. 218-262.