Comparison of GALS and synchronous architectures with MPEG-4 video encoder on multiprocessor system-on-chip FPGA

Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006

Volumn , Issue , 2006, Pages 83-86

  Kulmala, Ari ^a   Hämäläinen, Timo D ^a   Hännikäinen, Marko ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUITS; INTELLECTUAL PROPERTY; MULTIPROCESSING SYSTEMS;

CLOCK TREE REMOVAL; SYNCHRONOUS ARCHITECTURES; SYSTEM-ON-CHIP (SOC) ARCHITECTURES; VIDEO ENCODER;

IMAGE CODING;

EID: 34547985059     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2006.34     Document Type: Conference Paper

References (8)

1. A. Iyer and D. Marculescu, "Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors", Proc. 29th Annual International Symposium on Computer Architecture, IEEE, 2002, pp. 158-168.
2. G. Semenaro, D.H. Albonesi, G.Magklis, M.L. Scott, S.G. Dropsho, and D. Dwarkadas, "Hiding Synchronization Delays in a GALS Processor Microarchitecture", Proc. 10th International Symposium on Asynchronous Circuits and Systems, IEEE, 2004, pp. 159-169.
3. J. Muttersbach, T. Villiger, and W. Fichtner, "Practical Design of Globally-Asynchronous Locally-Synchronous Systems", Proc. Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE, 2000, pp. 52-59.
4. J. Quartana, S. Renane, A. Baixas, L. Fesquet, and M. Renaudin, "GALS System Prototyping Using Multiclock FPGAs and Asynchronous Network-on-Chips", Proc. International Conference on Field Programmable Logic and Applications, IEEE, 2005, pp. 299-304.
5. th Design Automation Conference, IEEE, 1999, pp. 873-878.
6. E. Salminen, V. Lahtinen, T. Kangas, J. Riihimäki, K. Kuusilinna, and T.D. Hämäläinen, "HIBI v.2 Communication Network for System-on-Chip", LNCS 3133 Computer Systems: Architectures, Modeling, and Simulation. A.D. Pimentel, S. Vassiliadis, (eds.). Springer-Verlag, Germany, July 2004, pp. 412-422.
7. A. Kulmala, T.D. Hämäläinen, and, M. Hännikäinen "Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA", Proc. International Conference on Field Programmable Logic and Applications, IEEE, 2006, Accepted.
8. O. Lehtoranta, E. Salminen, A. Kulmala, M. Hännikäinen, and T.D. Hämäläinen, "A parallel MPEG-4 encoder for FPGA based multiprocessor SoC", Proc. International Conference on Field Programmable Logic and Applications, IEEE, 2005, pp. 380-385.