Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates

IEEE Transactions on Microwave Theory and Techniques

Volumn 53, Issue 8, 2005, Pages 2472-2479

  Leung, Lydia Lap Wai ^a   Chen, Kevin J ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Microelectromechanical systems (MEMS); RF packaging; Silicon substrate; Through wafer interconnects (TWIs); Via holes

Indexed keywords

ASPECT RATIO; COMPUTER SIMULATION; MATHEMATICAL MODELS; MICROELECTROMECHANICAL DEVICES; MICROWAVES; NATURAL FREQUENCIES; OPTIMIZATION; SILICON WAFERS;

MEMS; RF PACKAGING; SILICON SUBSTRATES; THROUGH-WAFER INTERCONNECTS; VIA-HOLES;

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 24344491536     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2005.852782     Document Type: Article

References (17)

1. R. Ramesham and R. Ghaffarian, "Challenges in interconnect and packaging of microelectromechanical systems (MEMS)," in Proc. 50th Electronic Components Technology Conf., Piscataway, NJ, May 2000, pp. 666-675.
2. S. J. Ok, C. Kim, and D. Baldwin, "High density, high aspect-ratio through-wafer electrical interconnects vias for MEMS packaging," IEEE Trans. Compon., Packag., Manuf. Technol. B, vol. 26, no. 3, pp. 302-309. Aug. 2003.
3. K. M. Strohm, P. Nuechter, C. N. Rheinfelder, and R. Guehl, "Via-hole technology for microstrip transmission lines and passive elements on high resistivity silicon," in IEEE MTT-S Int. Microwave Symp. Dig., Boston, MA, 1999, pp. 581-584.
4. C. H. Cheng, A. S. Ergun, and B. T. Khuri-Yakub, "Electrical through-wafer interconnects with sub-picofarad parasitic capacitance," in Microelectromechanical Systems Conf., Interlaken, Switzerland, Aug. 2001, pp. 18-21.
5. E. M. Chow, V. C. Chandrasekaran, A. Partridge, T. Nishida, M. Sheplak, C. F. Quate, and T. W. Kenny, "Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrate," J. Microelectromech. Syst., vol. 11, no. 6, pp. 631-640, Dec. 2002.
6. S. Yamamoto, K. Itoi, T. Suemasu, and T. Takizawa, "Si through-hole interconnections filled with Au-Sn solder by molten metal suction method," in Proc. IEEE 16th Int. Microelectromechanical Systems Conf., Kyoto, Japan, Jan. 2003, pp. 642-645.
7. N. T. Nguyen, E. Boellaard, N. P. Pham, V. G. Kutchokov, G. Craciun, and P. M. Sarro, "Through-wafer copper electroplating for three-dimensional interconnects," J. Micromech. Microeng., vol. 12, pp. 395-399, Jun. 2002.
8. J. H. Wu, J. A. del Alamo, and K. A. Jenkins, "A high aspect-ratio silicon substrate-via technology and applications: Through-wafer interconnects for power and ground and faraday cages for SOC isolation," in Int. Electronic Devices Meeting Tech. Dig., San Francisco, CA, Dec. 2000, pp. 477-480.
9. L. Wang, A. Nichelatti, H. Schellevis, C. de Boer, C. Visser, T. N. Nguyen, and P. M. Sarro, "High aspect ratio through-wafer interconnections for 3-D microsystems," in Proc. IEEE 16th Int. Microelectromechanical Systems Conf., Kyoto, Japan, Jan. 2003, pp. 634-637.
10. R. Uscola and M. Tutt, "Determining the inductance of a through-substrate via using multiple on-wafer test approaches," in Proc. Int. Microelectronic Test Structures Conf., Hyogo, Japan, Mar. 2001, pp. 147-151.
11. L. L. W. Leung and K. J. Chen, "Microwave characterization of high aspect ratio through-wafer interconnect vias in silicon substrates," in IEEE MTT-S Int. Microwave Symp. Dig., Fort Worth, TX, 2004, pp. 1197-1200.
12. L. L. W. Leung, W. C. Hon, and K. J. Chen, "Low-loss coplanar waveguides interconnects on low-resistivity silicon substrate," IEEE Trans. Compon., Packag., Manuf. Technol., vol. 27, no. 3, pp. 507-512, Sep. 2004.
13. C. S. Premachandran, R. Nagarajan, C. Yu, Z. Xiolin, and C. S. Choong, "A novel electrically conductive wafer through hole filled vias interconnect for 3-D MEMS packaging," in Proc. 53th Electronic Components Technology Conf., New Orleans, LA, 2003, pp. 627-630.
14. D. G. Swanson and W. J. R. Hoefer, Microwave Circuit Modeling Using Electromagnetic Field Simulation, 1st ed. Boston, MA: Artech House, 2003.
15. M. E. Goldfarb and R. A. Pucel, "Modeling via-hole grounds in microstrip," IEEE Microw. Guided Wave Lett., vol. 1, no. 6, pp. 135-137, Jun. 1991.
16. A. R. Djordjevic, T. K. Sarkar, and S. M. Rao, "Analysis of finite conductivity cylindrical conductors excited by axially independent TM electromagnetic field," IEEE Trans. Microw. Theory Tech., vol. MTT-33, no. 10, pp. 960-966, Oct. 1985.
17. G. I. Costache, M. W. Nemes, and E. M. Petriu, "Finite element method analysis of the influence of the skin effect, proximity, and eddy currents on the internal magnetic field and impedance of a cylindrical conductor of arbitrary cross section," in Proc. Can. Electrical and Computer Engineering Conf., Quebec, QC, Canada, Sep. 1995, pp. 253-256.