High frequency electrical circuit model of chip-to-chip vertical via iterconnection for 3-D chip stacking package

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn 2005, Issue , 2005, Pages 151-154

  Ryu, Chunghyun ^a   Chung, Daehyun ^a   Lee, Junho ^a   Lee, Kwangyong ^b   Oh, Taesung ^b   Kim, Joungho ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b Hong Ik University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; ELECTRIC NETWORK ANALYSIS; EQUIVALENT CIRCUITS; FREQUENCIES; PARAMETER ESTIMATION;

MODEL PARAMETERS; PHYSICAL CONFIGURATION; VECTOR NETWORK ANALYZER;

NETWORKS (CIRCUITS);

EID: 33845882999     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2005.1563724     Document Type: Conference Paper

References (3)

1. M. Koyanagi, H. Kurino, K. Lee, K. Sakmicrona, N. Miyakawa, H. Itani, "Future System-on-Silicon LSI Systems", IEEE Micro, Vol. 18, No. 4, July-Aug. 1998, pp 17
2. st Electronic Components and Technology Conf., Orlando, FL., May 2001, pp 541-546
3. S. Ahn, J. Lee, J. Lee, J. Kim, W. Ryu, B.-H. Kmicron, H.-S. Choi, C. K. Yoon, and J. Kim, "Over GHz Electrical Circuit Model of a High-Density Multiple Line Grid Array(MLGA) Interposer, IEEE transaction on advanced packaging, Vol. 26.