Electrical modeling of annular and co-axial TSVs considering MOS capacitance effects

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09

Volumn , Issue , 2009, Pages 117-120

  Bandyopadhyay, Tapobrata ^a   Chatterjee, Ritwik ^a   Chung, Daehyun ^a   Swaminathan, Madhavan ^a   Tummala, Rao ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL MODELING; CAPACITANCE EFFECT; CO-AXIAL; DEPLETION REGION; ELECTRICAL MODELING; ELECTROMAGNETIC SIMULATION; LOW LOSS; METAL OXIDE SEMICONDUCTOR; PARAMETRIC STUDY;

ELECTRONICS PACKAGING; THREE DIMENSIONAL;

CAPACITANCE;

EID: 74549140252     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEPS.2009.5338462     Document Type: Conference Paper

References (6)

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2. Dong Min Jang, Chunghyun Ryu, Kwang Yong Lee, Byeong Hoon Cho, Joungho Kim, Tae Sung Oh, Won Jong Lee, and Jin Yu, "Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)," Proc. of ECTC 2007, pp. 847-52.
3. E.M. Chow, V. Chandrasekaran, A. Partridge, T. Nishida, M. Sheplak, C.F. Quate, and T.W. Kenny, "Process Compatible Polysilicon-Based Electrical Through-Wafer Interconnects in Silicon Substrates," Journal of MEMS, Vol. 11, No. 6, Dec. 2002, pp. 631-40.
4. T. Bandyopadhyay, R. Chatterjee, D. Chung, M. Swaminathan and R. Tummala, "Electrical Modeling of Through Silicon and Package Vias," 2009 IEEE International Conference on 3D System Integration (3D IC), San Francisco, California, USA.
5. E. H. Nicollian and J.R. Brews, MOS Physics and Technology, Wiley (1982).
6. Narain Arora, Mosfet Modeling for VLSI Simulation, World Scientific Publishing Co. Inc. (March 2007), pp. 150.