Thermally stable, sub-nanometer equivalent oxide thickness gate stack for gate-first In 0.53Ga 0.47As metal-oxide-semiconductor field-effect-transistors

Applied Physics Letters

Volumn 100, Issue 6, 2012, Pages

  El Kazzi, M ^a   Czornomaz, L ^a   Rossel, C ^a   Gerl, C ^a   Caimi, D ^a   Siegwart, H ^a   Fompeyrine, J ^a   Marchiori, C ^a  

^a IBM RESEARCH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

BARRIER LAYERS; ELECTRICAL CHARACTERISTIC; EQUIVALENT OXIDE THICKNESS; FABRICATION PROCESS; GATE STACKS; METAL OXIDE SEMICONDUCTOR; MID-GAP INTERFACES; MOBILITY VALUE; PASSIVATING LAYER; POST-METALLIZATION ANNEAL; SELF-ALIGNED; SOURCE AND DRAINS; THERMALLY STABLE; VOLTAGE CHARACTERISTICS;

ALUMINUM; DIELECTRIC DEVICES; FABRICATION; FIELD EFFECT TRANSISTORS; GALLIUM; HAFNIUM OXIDES; LOGIC GATES; MOS CAPACITORS; SILICON; THERMODYNAMIC STABILITY;

SEMICONDUCTING SILICON;

EID: 84857214855     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.3683472     Document Type: Article

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