Self-aligned S/D regions for InGaAs MOSFETs

European Solid-State Device Research Conference

Volumn , Issue , 2011, Pages 219-222

  Czornomaz, L ^a   El Kazzi, M ^a   Caimi, D ^a   Machler P ^a   Rossel, C ^a   Bjoerk, M ^a   Marchiori, C ^a   Fompeyrine, J ^a  

^a IBM RESEARCH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

DIFFERENT PROCESS; INDIUM GALLIUM ARSENIDE; INTEGRATION ISSUES; METAL CONTACTS; METAL OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTORS; METAL-ORGANIC VAPOR PHASE EPITAXY; MOSFETS; SELF-ALIGNED; SOURCE/DRAIN REGIONS;

EPITAXIAL GROWTH; FIELD EFFECT TRANSISTORS; GALLIUM ARSENIDE; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTING INDIUM; SILICIDES; VANADIUM; X RAY PHOTOELECTRON SPECTROSCOPY;

METALLORGANIC VAPOR PHASE EPITAXY;

EID: 82955195062     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2011.6044195     Document Type: Conference Paper

References (7)

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6. M. El Kazzi et al., "1.2 nm capacitance equivalent thickness gate stacks on Si-passivated GaAs", Microelec. Eng., in press.
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