Junction-level thermal analysis of 3-d integrated circuits using high definition power blurring

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 31, Issue 5, 2012, Pages 676-689

  Melamed, Samson ^a   Thorolfsson, Thorlindur ^b   Harris, T Robert ^c   Priyadarshi, Shivam ^d   Franzon, Paul ^d   Steer, Michael B ^d   Davis, W Rhett ^d  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

^b SYNOPSYS INC   (United States)

^c Dot Metrics Technologies Inc   (United States)

^d North Carolina State University   (United States)

Author keywords

3 D integrated circuits (3DICs); measurement; Power Blurring method; silicon on insulator (SOI); simulation; thermal analysis; through silicon vias (TSVs)

Indexed keywords

3-D INTEGRATED CIRCUIT; POWER BLURRING METHOD; SILICON-ON-INSULATORS; SIMULATION; THROUGH SILICON VIAS;

INTEGRATED CIRCUITS; MEASUREMENTS; SYNTHETIC APERTURE RADAR; THERMOANALYSIS; THREE DIMENSIONAL; THREE DIMENSIONAL COMPUTER GRAPHICS;

DIGITAL TELEVISION;

EID: 84856819102     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2011.2180384     Document Type: Article

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