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1
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0033699518
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Multiple Si layer ICs: Motivation, performance analysis, and design implications
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Los Angeles, California, June
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S. J. Souri, K. Banerjee, A. Mehrotra, and K. C. Saraswat, "Multiple Si layer ICs: motivation, performance analysis, and design implications," 37th Design Automation Conf. (DAC), Los Angeles, California, June 2000, pp. 873-880.
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(2000)
37th Design Automation Conf. (DAC)
, pp. 873-880
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Souri, S.J.1
Banerjee, K.2
Mehrotra, A.3
Saraswat, K.C.4
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2
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33747566850
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3-D ICs: A novel chip design for improving deep submicron interconnect performance and systems-on-chip integration
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May
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K. Banerjee, S. J. Souri, P. Kapur, K. C. Saraswat, "3-D ICs: A novel chip design for improving deep submicron interconnect performance and systems-on-chip integration," Proc. IEEE, Special Issue on Interconnects, May 2001, pp.602-633.
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(2001)
Proc. IEEE, Special Issue on Interconnects
, pp. 602-633
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Banerjee, K.1
Souri, S.J.2
Kapur, P.3
Saraswat, K.C.4
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3
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0034452632
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Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs
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Sungjun Im and K. Banerjee, "Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs", Tech. Digest IEDM, 2000, pp.727-730.
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(2000)
Tech. Digest IEDM
, pp. 727-730
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Im, S.1
Banerjee, K.2
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4
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0035715858
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Thermal analysis of heterogeneous 3-D ICs with various integration scenarios
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T.Y. Chiang, S.J. Souri, C.O. Chui, and K.C. Saraswat, "Thermal Analysis of Heterogeneous 3-D ICs with Various Integration Scenarios", Technical Dig. IEDM, 2001, pp.681-684.
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(2001)
Technical Dig. IEDM
, pp. 681-684
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Chiang, T.Y.1
Souri, S.J.2
Chui, C.O.3
Saraswat, K.C.4
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7
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6344232093
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CFD-micromesh: A fast geometrical modeling and mesh generation tool for 3-D microsystem simulations
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San Diego, California, March 27-29
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Z.Q. Tan, M. Furmanczyk, M. Turowski, and A. Przekwas, "CFD-Micromesh: A Fast Geometrical Modeling and Mesh Generation Tool for 3-D Microsystem Simulations", Int. Conf. MSM 2000, San Diego, California, March 27-29, 2000, pp.712-715
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(2000)
Int. Conf. MSM 2000
, pp. 712-715
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Tan, Z.Q.1
Furmanczyk, M.2
Turowski, M.3
Przekwas, A.4
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8
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0033871060
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Ceil-level placement for improving substrate thermal distribution
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February
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Tsai, Ching-Han and Kang, Sung-Mo (Steve), "Ceil-Level Placement for Improving Substrate Thermal Distribution", IEEE Trans Computer-aided Design of Integrated Circuits and Systems, Vol. 19, No. 2, February 2000.
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(2000)
IEEE Trans Computer-aided Design of Integrated Circuits and Systems
, vol.19
, Issue.2
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Tsai, C.-H.1
Kang, S.-M.2
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9
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1942440425
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Layout based full chip thermal simulations of stacked 3D integrated circuits
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Washington, D.C., November 16-21
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Ashok Raman, Marek Turowski, Patrick Wilkerson, "Layout Based Full Chip Thermal Simulations of Stacked 3D Integrated Circuits", Proceedings of IMECE'03, 2003 ASME International Mechanical Engineering Congress & Exposition, Washington, D.C., November 16-21, 2003.
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(2003)
Proceedings of IMECE'03, 2003 ASME International Mechanical Engineering Congress & Exposition
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Raman, A.1
Turowski, M.2
Wilkerson, P.3
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10
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85043042855
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Full-chip 3D thermal simulation of stacked IC's
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Lodz, Poland, 30 June - 2 July
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Marek Turowski, Ashok Raman, Monte Mar, "Full-chip 3D Thermal Simulation of Stacked IC's", International Conference on Thermal Problems in Electronics, MICROTHERM 2003, Lodz, Poland, 30 June - 2 July, 2003.
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(2003)
International Conference on Thermal Problems in Electronics, MICROTHERM 2003
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Turowski, M.1
Raman, A.2
Mar, M.3
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