Coupled simulation of device performance and heating of vertically stacked three-dimensional integrated circuits

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn 2005, Issue , 2005, Pages 115-118

  Akturk, Akin ^a   Goldsman, Neil ^a   Metze, George ^b  

^a UNIVERSITY OF MARYLAND   (United States)

^b LABORATORY FOR PHYSICAL SCIENCES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY CONDITIONS; COMPUTER SIMULATION; COOLING; MICROPROCESSOR CHIPS; MONTE CARLO METHODS; NUMERICAL METHODS; TEMPERATURE DISTRIBUTION;

HEAT GENERATION; NONISOTHERMAL DEVICES; THERMAL COUPLING;

INTEGRATED CIRCUIT LAYOUT;

EID: 33748533215     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/sispad.2005.201486     Document Type: Conference Paper

References (5)

1. S S. Im, K. Banerjee, "Full Chip Thermal Analysis of Planar (2D) and Vertically Stacked Integrated (3D) High Performance ICs," IEDM, pp. 727-30, 2000.
2. P, Gelsinger. "Microprocessors for the new Millenium: Challenges, Opportunities, and New Frontiere," ISSCC, pp. 22-5, 2001.
3. A. Akturk, N. Goldsman and G. Metze, "Coupled Modeling of Time-Dependent Full-Chip Heating and Quantum Non-Isothermal Device Operation," SISPAD, pp. 311-4, 2003.
4. http://www.intel.com
5. S. S. Lee and D. J. Allstot, "Electrothermal Simulation of Integrated Circuits," Solid-Stale Circuits, vol. 28, iss. 12, pp. 1283-93, 1993.