Fast thermal analysis of vertically integrated circuits (3-D ICS) using power blurring method

Proceedings of the ASME InterPack Conference 2009, IPACK2009

Volumn 2, Issue , 2010, Pages 701-707

  Park, Je Hyoung ^a   Shakouri, Ali ^a   Kang, Sung Mo ^b  

^a University of California Santa Cruz   (United States)

^b University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; ACTIVE LAYER; CHIP STRUCTURES; CMOS VLSI TECHNOLOGY; COMPUTATION METHODS; COMPUTATION TIME; CONVOLUTION TECHNIQUES; FEA SOFTWARE; FEATURE SIZES; GRID-BASED; HOLISTIC MANNER; IC CHIPS; IC TECHNOLOGY; INTERCONNECT TECHNOLOGY; MATRIX; MAXIMUM ERROR; ON CHIP INTERCONNECT; POWER DISSIPATION; SCALE DOWN; TECHNICAL CHALLENGES; TEMPERATURE PROFILES; THERMAL ANALYSIS; THERMAL-AWARE DESIGN;

COMPUTATIONAL EFFICIENCY; CONVOLUTION; ECONOMIC ANALYSIS; INTEGRATED CIRCUITS; INTELLIGENT CONTROL; INTERCONNECTION NETWORKS; TECHNOLOGY; TEMPERATURE CONTROL; THERMOANALYSIS;

THREE DIMENSIONAL;

EID: 77953918475     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1115/InterPACK2009-89072     Document Type: Conference Paper

References (16)

1. T. S. Cale, J. -Q. Lu, and R. J. Gutmann, "Three-Dimensional Integration in Microlectronics: Motivation, Processing, and Thermomechanical Modeling," Chemical Engineering Communications, vol. 195, no. 8, Aug. 2008, pp. 847-888.
2. International Technology Roadmap for Semiconductors (ITRS). [Online]. Available:http://www.itrs.net.
3. th ACM Design Automation Conference (DAC), New Orleans, LA, Jun. 1999, pp. 885-891.
4. S. Rzepka, K. Banerjee, E. Meusel, and C. Hu, "Characterization of Self-Heating in Advanced VLSI Interconnect Lines Based on Thermal Finite Element Simulation," IEEE Trans. Components, Packagin, and Manufacturing Technology - Part A, vol. 21, no. 3, Sep. 1998, pp. 406-411.
5. K. Banerjee, "Trends for ULSI Interconnections and Their Implications for Thermal, Reliability and Performance Issues," International Dielectrics and Conductors for ULSI Multilevel Interconnection Conference (DCMIC), Santa Clara, Mar. 2001, pp. 38-50.
6. S. Chong, L. Shang, and R. P. Dick, "Three-dimensional multi-processor system-on-chip thermal optimization," Proc. International Conference Hardware/Software Codesign and System Synthesis, Sep. 2007.
7. J. -Q. Lu, Y. Kwon, G. Rajagopalan, M. Gupta, J. McMahon, K. -W. Lee, R. P. Kraft, J. F. McDonald, T. S. Cale, R. J. Gutmann, B. Xu, E. Eisenbraun, J. Castracane, and A. Kaloyeros, "A Wafer-Scale 3D IC Technology Platform using Dielectric Bonding Glues and Copper Damascene Patterned Inter-Wafer Interconnects," Proc. of IEEE International Technology Conference, Jun 2002, pp. 78-80.
8. K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, "3-D ICs: A Novel Chip Design for Improving Deep Submicron Interconnect Performance and Systems-On-Chip Integration," Proc. the IEEE, Special Issue, Interconnections-Addressing The Next Challenge of IC Technology, vol. 89, no. 5, 2001. pp. 602-633.
9. R. S. Parti, "Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs," Proc. of IEEE, vol. 94, no. 6, June 2006, pp. 1214-1224.
10. T. Kemper, Y. Zhang, Z. Bian, and A. Shakouri, "Ultrafast Temperature Profile Calculation in IC chips," Proc. of 12th International Workshop on Thermal investigations of ICs (THERMINIC), Nice, France, 2006, pp. 133-137.
11. Virginia Martin Heriz, Je-Hyoung Park, Ali Shakouri, and Sung-Mo Kang, "Method of Images for the Fast Calculation of Temperature Distributions in Packaged VLSI Chips," Proceedings of 13th International Workshop on Thermal investigations of ICs (THERMINIC), Budapest, Hungary, September 17-19, 2007.
12. S. Moghaddam, K. T. Kiger, A. Modafe, and R. Ghodssi, "A Novel Benzocyclobutene-Based Device for Studying the Dynamics of Heat Transfer During the Nucleation Process," Journal of Microelectromechanical systems, vol. 16, no. 6, Dec. 2007, pp. 1355-1366.
13. th Edition, 1984.
14. C. A. Balanis, "Advanced Engineering Electromagnetics," John Wiley & Sons, New York, 1989, chap. 14.
15. ANSYS R11.0, Swanson ANSYS Inc., 2007.
16. Je-Hyoung Park, Virginia Martin Heriz, Ali Shakouri, and Sung-Mo Kang, "Ultra Fast Calculation of Temperature Profiles of VLSI ICs in Thermal Packages Considering Parameter Variations," IMAPS 40th International Symposium on Microelectronics, San Jose, Nov. 11-15, 2007.