Fast evaluation method for transient hot spots in VLSI ICs in packages

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Volumn , Issue , 2008, Pages 600-603

  Park, Je Hyoung ^a   Shakouri, Ali ^a   Kang, Sung Mo ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CASE STUDIES; CHIP-LEVEL; COMPUTATION TIME; COMPUTATIONAL EXPENSES; ELECTRONIC DESIGNS; FAST EVALUATION; HIGH POWER CHIPS; HOT SPOTTING; IC DESIGNS; INDUSTRY STANDARDS; INTERNATIONAL SYMPOSIUM; MAXIMUM ERROR; TEMPERATURE NON UNIFORMITIES; TEMPERATURE PROFILING; TRANSIENT TEMPERATURES; WORST CASE;

CONVOLUTION; ELECTRONICS ENGINEERING; STANDARDS;

FINITE ELEMENT METHOD;

EID: 49749109152     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2008.4479805     Document Type: Conference Paper

References (5)

1. International Technology Roadmap for Semiconductors (ITRS), Semiconductor Industry Association, 2006 update.
2. Ting-Yuan Wang and Charlie Chung-Ping Chen, "Thermal-ADI - A Linear-Time Chip-Level Dynamic Thermal-Simulation Algorithm Based on Alternating-Direction-Implicit (ADI) Method," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 4, August 2003.
3. Sheng-Chih Lin and Kaustav Banerjee, "An Electrothermally-Aware Full-Chip Substrate Temperature Gradient Evaluation Methodology for Leakage Dominant Technologies with Implication for Power Estimation and Hot-Spot Management," International Conference on Computer-Aided Design, San Jose, CA, November 5-9 2006.
4. Travis Kemper, Yan Zhang, Zhixi Bian, and Ali Shakouri, "Ultrafast Temperature Profile Calculation in IC chips," Proceedings of 12th International Workshop on Thermal investigations of ICs (THERMINIC), Nice, France, pp. 133-137, 2006.
5. ANSYS R11.0, Swanson ANSYS Inc., 2007