Wire-bonded through-silicon vias with low capacitive substrate coupling

Journal of Micromechanics and Microengineering

Volumn 21, Issue 8, 2011, Pages

  Fischer, A C ^a   Grange, M ^b   Roxhed, N ^a   Weerasekera, R ^b   Pamunuwa, D ^b   Stemme, G ^a   Niklaus, F ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

^b LANCASTER UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITIVE COUPLINGS; EMERGING TECHNOLOGIES; GOLD WIRE; LOWER COST; NOVEL TECHNIQUES; PARASITIC CAPACITANCE; SIGNAL PATH LENGTH; STACKED DIE; SUBSTRATE COUPLINGS; THERMO-MECHANICAL STRESS; THREE DIMENSIONAL INTEGRATION; THROUGH SILICON VIAS;

STRESSES;

WIRE;

EID: 79961219588     PISSN: 09601317     EISSN: 13616439     Source Type: Journal    
DOI: 10.1088/0960-1317/21/8/085035     Document Type: Article

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