A novel capillary-effect-based solder pump structure and its potential application for through-wafer interconnection

Journal of Micromechanics and Microengineering

Volumn 19, Issue 7, 2009, Pages

  Gu, Jiebin ^a   Pike, W T ^a   Karl, W J ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCED PACKAGING; CONDUCTIVE PATHS; CRITICAL TECHNOLOGIES; ELECTRICAL INTERCONNECTIONS; ETCHED HOLES; FLOW PATH; METALLIZATION; MOLTEN SOLDERS; POTENTIAL APPLICATIONS; PRESSURE DIFFERENTIAL; PUMP STRUCTURE; SILICON DIE; THROUGH-WAFER INTERCONNECTS; VIA HOLE; WAFER INTERCONNECTIONS;

BRAZING; DIES; PUMPS; SILICON WAFERS; SURFACE TENSION; WELDING;

ELECTRONICS PACKAGING;

EID: 67849133472     PISSN: 09601317     EISSN: 13616439     Source Type: Journal    
DOI: 10.1088/0960-1317/19/7/074005     Document Type: Article

References (20)

1. Jozwiak J, Southwick R G, Johnson V N, Knowlton W B and Moll A J 2008 Integrating Through-wafer interconnects with active devices and circuits, advanced packaging IEEE Trans. 31 4-13
2. Yue C P, Mccarthy A, Ryu C, Lee T H, Wong S S and Quate C F 1999 Ultra-low resistance, through-wafer via (TWV) technology and its applications in three dimensional structures on silicon Japan. J. Appl. Phys. 38 2393-6
3. Neysmith J 2001 Modular, device-scale, direct-chip-attach packaging for microsystems IEEE Trans. Compon. Packag. Technol. 24 631-4 (see also Compon. Packag. Manuf. Technol. Part A: Packaging Technologies)
4. Ok J S 2003 IEEE Trans. Adv. Packag. 26 302-9 (see also IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging,)
5. Hilbert C, Nelson R, Reed J, Lunceford B, Somadder A, Hu K and Ghoshal U 1999 Thermoelectric MEMS Coolers pp 117-22
6. Wu J H 2004 A through-wafer interconnects in silicon for rfics Electron. Devices IEEE Trans. 51 1765-71
7. Lin C-W, Yang H-A, Wang W C and Fang W 2007 Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections J. Micromech. Microeng. 1200-5
8. Saadaoui M 2007 Local sealing of high aspect ratio vias for single step bottom-up copper electroplating of through wafer interconnects Proc. IEEE Sensors 2007 Conf. pp 974-7
9. Jozwiak J 2008 Integrating through-wafer interconnects with active devices and circuits IEEE Trans. Adv. Packag. 31 4-13 (see also IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging)
10. Lin C-W 2008 Implementation of SOG devices with embedded through-wafer silicon vias using a glass reflow process for wafer-level 3D MEMS integration IEEE 21st Int. Conf. on Micro Electro Mechanical Systems (Tucson, Az) ed C-P Hsu (Piscataway, NJ: IEEE) pp 802-5
11. Leung L L W and Chen K J 2005 Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates IEEE Trans. Microw. Theory Tech. 53 2472-80
12. Tian J, Iannacci J, Sosin S, Gaddi R and Bartek M 2006 Rf-MEMS wafer-level packaging using through-wafer via technology 8th Electronics Packaging Technology Conf., 2006 EPTC '06 pp 441-7
13. Rimskog M 2007 Through wafer via technology for MEMS and 3D integration. 32nd IEEE/CPMT International Electronic Manufacturing Technology Symp. 2007 IEMT '07 pp 286-9
14. This technique has been filed for granting a patent, Application Number GB reference number: P45708/JEP
15. Alexandrou A 2001 Principles of Fluid Mechanics 1st edn (Englewood Cliffs, NJ: Prentice-Hall) p 237 Chapter 7
16. Pape U and Schulz J-U 2006 Characteristics of lead-free solders during flow soldering (selective and wave soldering) 1st Electronics System Integration Technology Conf. 2006 vol 1 pp 139-44
17. Kaban I, Mhiaoui S, Hoyer W and Gasser J-G 2005 Surface tension and density of binary lead and lead-free Sn-based solders J. Phys.: Condens. Matter. 17 7867-73
18. Schilp A and Laermer F 1996 Method of anisotropically etching silicon US Patent US5501893 Robert Bosch GmbH (March 26 1996)
19. http://www.senju-m.co.jp/en/product/ecosolder/index.html
20. www.chipscalereview.com/archives/ES/issues/1102/solder-ball-placement.pdf