Development of vertical and tapered via etch for 3D through wafer interconnect technology

Proceedings of the Electronic Packaging Technology Conference, EPTC

Volumn , Issue , 2006, Pages 22-28

  Tezcan, Deniz Sabuncuoglu ^a   De Munck, Koen ^a   Pham, Nga ^a   Luhn, Ole ^a   Aarts, Arno ^a   De Moor, Piet ^a   Baert, Kris ^a   Van Hoof, Chris ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ARGON; ASPECT RATIO; CHIP SCALE PACKAGES; CLADDING (COATING); CURING; DRYING; ELECTRON BEAM LITHOGRAPHY; ELECTRONICS PACKAGING; LEAKAGE CURRENTS; MATHEMATICAL MODELS; NONMETALS; OPTICAL DESIGN; PASSIVATION; PHOTORESISTS; POLYSILICON; PRESSURE DROP; SILICA; SILICON COMPOUNDS; SILICON WAFERS; TECHNOLOGY; THREE DIMENSIONAL;

DEEP REACTIVE ION ETCH; ELECTRICAL INTERCONNECTS; ETCH PARAMETERS; FABRICATED DEVICES; GENERIC APPROACHES; HIGH ASPECT RATIO; INTERCONNECT TECHNOLOGIES; LINEAR MODELING; MASKLESS; PACKAGING TECHNOLOGIES; REACTIVE ION; SIDE WALL ROUGHNESS; SILICON ETCHING; SILICON OXIDES; SLOPE ANGLES; TWO TYPES; WET AND DRY;

ELECTRONIC EQUIPMENT MANUFACTURE;

EID: 49749117213     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2006.342685     Document Type: Conference Paper

References (11)

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