Novel through-silicon via technique for 2d/3d SiP and interposer in low-resistance applications

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2009, Pages 1796-1801

  Nilsson, P ^a   Ljunggren, A ^a   Thorslund, R ^a   Hagstrom M ^a   Lindskog, V ^a  

^a Angstrom Aerospace Corporation   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

3D SYSTEMS; CLOCK RATE; COPPER SEED; DRIE ETCHING; ENVIRONMENTAL TEST; HEAT DISSIPATION; HIGH YIELD; IMPEDANCE CONTROL; IN-PLANE; LOW RESISTANCE; MECHANICAL ROBUSTNESS; METAL DEPOSITION; POWER DISSIPATION; PULL STRENGTH; RC DELAY; RE-DISTRIBUTION; RESISTANCE MEASUREMENT; SI WAFER; SIGNAL PATHS; SILICON SUBSTRATES; THROUGH SILICON VIAS; VIA TECHNOLOGIES;

ELECTRONICS PACKAGING; ENVIRONMENTAL TESTING; INTERNET PROTOCOLS; SHEAR STRENGTH; SILICON WAFERS;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 70349672835     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2009.5074261     Document Type: Conference Paper

References (3)

1. th Electronics Packaging Technology Conference, Singapore, December 2008.
2. th Electronic Components & Technology Conference, Florida USA, May 2008.
3. Kutchoukov V G, Fabrication Technology for Through- Wafer Interconnects, Eburon Publishers, (The Netherlands, 2002).