Low-cost Through Silicon Vias (TSVs) with wire-bonded metal cores and low capacitive substrate-coupling

Proceedings of the IEEE International Conference on Micro Electro Mechanical Systems (MEMS)

Volumn , Issue , 2010, Pages 480-483

  Fischer, A C ^a   Roxhed, N ^a   Stemme, G ^a   Niklaus, F ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITIVE COUPLINGS; CONDUCTIVE PATHS; EMERGING TECHNOLOGIES; LOW COST FABRICATION; LOWER COST; METAL CORE; PARASITIC CAPACITANCE; SIGNAL LENGTH; STACKED DIE; THERMO-MECHANICAL STRESS; THREE DIMENSIONAL (3D) INTEGRATION; THROUGH SILICON VIAS;

MECHANICAL ENGINEERING; REACTIVE ION ETCHING; THREE DIMENSIONAL; WIRE;

STRESSES;

EID: 77952772699     PISSN: 10846999     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MEMSYS.2010.5442460     Document Type: Conference Paper

References (9)

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