Direct Measurement of Correlation between SRAM noise margin and individual cell transistor variability by using device matrix array

IEEE Transactions on Electron Devices

Volumn 58, Issue 8, 2011, Pages 2249-2256

  Hiramoto, Toshiro ^a,b   Suzuki, Makoto ^a   Song, Xiaowei ^a   Shimizu, Ken ^a   Saraya, Takuya ^a   Nishida, Akio ^b   Tsunomura, Takaaki ^b   Kamohara, Shiro ^b   Takeuchi, Kiyoshi ^b   Mogami, Tohru ^b  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

^b SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

Author keywords

Cell stability; metal oxide semiconductor (MOS) field effect transistor; static noise margin (SNM); threshold voltage variability

Indexed keywords

CELL STABILITY; CELL TRANSISTOR; DIRECT MEASUREMENT; INDIVIDUAL CELLS; LOW SUPPLY VOLTAGES; MATRIX ARRAYS; METAL OXIDE SEMICONDUCTOR; NOISE MARGINS; SRAM CELL; SRAM STABILITY; STATIC NOISE MARGIN; STATIC NOISE MARGIN (SNM); STATIC RANDOM ACCESS MEMORY; SUPPLY VOLTAGES; TEST ELEMENT GROUPS; THRESHOLD VOLTAGE VARIABILITY;

CELLS; CIRCUIT SIMULATION; FIELD EFFECT TRANSISTORS; THRESHOLD VOLTAGE; TRANSISTORS; VANADIUM;

STATIC RANDOM ACCESS STORAGE;

EID: 79960847838     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2138142     Document Type: Article

References (30)

1. B. Hoeneisen and C. A. Mead, "Fundamental limitations in microelectronics-I. MOS technology," Solid State Electron., vol. 15, no. 7, pp. 819-829, Jul. 1972.
2. R. W. Keyes, "The effect of randomness in the distribution of impurity atoms on FET thresholds," Appl. Phys., vol. 8, no. 3, pp. 251-259, Nov. 1975.
3. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989.
4. H.-S. Wong and Y. Taur, "Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 μm MOSFETs," in IEDM Tech. Dig., 1993, pp. 705-708.
5. T.Mizuno, J. Okamura, and A. Toriumi, "Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs," IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 2216-2221, Nov. 1994.
6. A. Asenov, "Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFETs: A 3-D "atomistic" simulation study," IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2505-2513, Dec. 1998. (Pubitemid 128736693)
7. K. Takeuchi, T. Tatsumi, and A. Furukawa, "Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation," in IEDM Tech. Dig., 1997, pp. 841-844.
8. Y. Yasuda, M. Takamiya, and T. Hiramoto, "Separation of effects of statistical impurity number fluctuations and position distribution on Vth fluctuations in scaled MOSFETs," IEEE Trans. Electron Devices, vol. 47, no. 10, pp. 1838-1842, Oct. 2000.
9. A. Asenov, S. Kaya, and A. R. Brown, "Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness," IEEE Trans. Electron Devices, vol. 50, no. 5, pp. 1254-1260, May 2003.
10. K. Takeuchi, T. Fukai, T. Tsunomura, A. T. Putra, A. Nishida, S. Kamohara, and T. Hiramoto, "Understanding random threshold voltage fluctuation by comparing multiple fabs and technologies," in IEDM Tech. Dig., 2007, pp. 467-470.
11. K. J. Kuhn, "Reducing variation in advanced logic technologies: Approaches to process and design for manufacturability of nanoscale CMOS," in IEDM Tech. Dig., 2007, pp. 471-474.
12. T. Tsunomura, A. Nishida, and T. Hiramoto, "Analysis of NMOS and PMOS difference in VT variation with large-scale DMA-TEG," IEEE Trans. Electron Devices, vol. 56, no. 9, pp. 2073-2080, Sep. 2009.
13. A. T. Putra, A. Nishida, S. Kamohara, and T. Hiramoto, "Random threshold voltage variability induced by gate-edge fluctuations in nanoscale metal-oxide-semiconductor field-effect transistors," Appl. Phys. Express, vol. 2, no. 2, p. 024501, Jan. 2009.
14. A. T. Putra, A. Nishida, S. Kamohara, T. Tsunomura, and T. Hiramoto, "Consideration of random dopant fluctuation models for accurate prediction of threshold voltage variation of metal-oxide-semiconductor field effect-transistors in 45 nm technology and beyond," Jpn. J. Appl. Phys., vol. 48, no. 4, p. 044502, Apr. 2009.
15. A. T. Putra, T. Tsunomura, A. Nishida, S. Kamohara, K. Takeuchi, and T. Hiramoto, "Impact of oxide thickness fluctuation and local gate depletion on threshold voltage variation in metal-oxide-semiconductor field-effect- transistors," Jpn. J. Appl. Phys., vol. 48, no. 6, p. 064504, Jun. 2009.
16. T. Tsunomura, A. Nishida, and T. Hiramoto, "Investigation of threshold voltage variability at high temperature using Takeuchi plot," Jpn. J. Appl. Phys., vol. 49, no. 5, p. 054101, May 2010.
17. T. Tsunomura, A. Nishida, and T. Hiramoto, "Effect of channel dopant profile on difference in threshold voltage variability between NFETs and PFETs," IEEE Trans. Electron Devices, vol. 57, no. 2, pp. 364-369, Feb. 2011.
18. A. J. Bhavnagarwala, X. Tang, and J. D. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 658-665, Apr. 2001. (Pubitemid 32407171)
19. F. Tachibana and T. Hiramoto, "Re-examination of impact of intrinsic dopant fluctuations on SRAM static noise margin," Jpn. J. Appl. Phys., vol. 44, pt. 1, no. 4B, pp. 2147-2151, Apr. 2005. (Pubitemid 40892637)
20. A. Bhavnagarwala, S. Kosonocky, C. Radens, K. Stawiasz, R. Mann, Q. Ye, and K. Chin, "Fluctuation limits & scaling opportunities for CMOS SRAM cells," in IEDM Tech. Dig., Dec. 2005, pp. 659-662. (Pubitemid 46370937)
21. M. Suzuki, T. Saraya, K. Shimizu, T. Sakurai, and T. Hiramoto, "Post-fabrication self-convergence scheme for suppressing variability in SRAM cells and logic transistors," in VLSI Symp. Tech. Dig., Jun. 2009, pp. 148-149.
22. X. Zhang, J. Li, M. Grubbs, M. Deal, B. Magyari-Köpe, B. Clemens, and Y. Nishi, "Physical model of the impact of metal grain work function variability on emerging dual metal gate MOSFETs and its implication for SRAM reliability," in IEDM Tech. Dig., Dec. 2009, pp. 57-60.
23. A. Katayama, T. Yabe, O. Hirabayashi, Y. Takeyama, K. Kushida, T. Sasaki, and N. Otsuka, "Direct cell-stability test techniques for an SRAM macro with asymmetric cell-bias-voltage modulation," in Proc. Int. Test Conf., 2008, pp. 1-7.
24. Z. Guo, A. Carlson, L.-T. Pang, K. Duong, T.-J.K. Liu, and B. Nikolic, "Large-scale SRAM variability characterization in 45 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3174-3192, Nov. 2009.
25. X. Deng,W. K. Loh, B. Pious, T.W. Houston, L. Liu, B. Khan, D. Corum, J. Raval, J. Gertas, F.-Y. Rousey, J. Steck, C. Suwannakinthorn, and R. McKee, "Characterization of bit transistors in a functional SRAM," in Proc. VLSI Circuits Symp., 2008, pp. 44-45.
26. H. Fujiwara, S. Okumura, Y. Iguchi, H. Noguchi, H. Kawaguchi, and M. Yoshimoto, "A dependable SRAM with 7T/14T memory cells," IEICE Trans. Electron., vol. E92-C, no. 4, pp. 423-432, Apr. 2009.
27. M. Suzuki, T. Saraya, K. Shimizu, A. Nishida, S. Kamohara, K. Takeuchi, S. Miyano, T. Sakurai, and T. Hiramoto, "Direct measurements, analysis, and post-fabrication improvement of noise margins in SRAM cells utilizing DMA SRAM TEG," in VLSI Symp. Tech. Dig., Jun. 2010, pp. 191-192.
28. T. Tsunomura, A. Nishida, and T. Hiramoto, "Verification of threshold voltage variation properties in scaled transistors with ultra large-scale device matrix array test element group," Jpn. J. Appl. Phys., vol. 48, no. 12, p. 124505, Dec. 2009.
29. T. Tsunomura, A. Kumar, T. Mizutani, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, and T. Mogami, "Origin of larger drain current variability in N-type field-effect transistors analyzed by variability decomposition method," Appl. Phys. Express, vol. 3, no. 11, p. 114201, Nov. 2010.
30. M. Miyamura, T. Nagumo, K. Takeuchi, K. Takeda, andM. Hane, "Effects of drain bias on threshold voltage fluctuation and its impact on circuit characteristics," in IEDM Tech. Dig., Dec. 2008, pp. 447-450.