Analysis of NMOS and PMOS difference in VT variation with large-scale DMA-TEG

IEEE Transactions on Electron Devices

Volumn 56, Issue 9, 2009, Pages 2073-2080

  Tsunomura, Takaaki ^a   Nishida, Akio ^a   Hiramoto, Toshiro ^a,b  

^a SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

^b INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

Boron; Doping; MOSFETs; Threshold voltage; Variation

Indexed keywords

CHANNEL STRAIN; CLUSTERING MODEL; DOMINANT FACTOR; DOPANT FLUCTUATION; DOPING; ELECTRICAL ANALYSIS; GATE DEPLETION; GATE LENGTH; GATE OXIDE THICKNESS; GATE WIDTHS; GATE-OXIDE INTERFACE; MOSFETS; PHYSICAL ANALYSIS; PHYSICAL PARAMETERS; POLY-SI GRAINS; PROCESS PARAMETERS; RANDOM CHANNEL; RDF MODEL; TAPER ANGLES; VARIATION;

BORON COMPOUNDS; DOPING (ADDITIVES); GATES (TRANSISTOR); MOSFET DEVICES; POLYSILICON; THRESHOLD VOLTAGE;

BORON;

EID: 69549086241     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2026390     Document Type: Article

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