Investigation of threshold voltage variability at high temperature using Takeuchi plot

Japanese Journal of Applied Physics

Volumn 49, Issue 5 PART 1, 2010, Pages 0541011-0541016

  Tsunomura, Takaaki ^a   Nishida, Akio ^a   Hiramoto, Toshiro ^a,b  

^a Research Dept 2   (Japan)

^b INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL DEPLETION; HIGH TEMPERATURE; MATRIX ARRAYS; METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR; MOSFETS; NORMAL PROBABILITY PLOT; NORMAL PROPERTIES; NORMALIZATION METHODS; ROOM TEMPERATURE; STRONG CORRELATION; TEMPERATURE DEPENDENCE; TEST ELEMENT GROUPS; THRESHOLD VOLTAGE VARIABILITY; VARYING TEMPERATURE;

ELECTRONIC EQUIPMENT TESTING; MOSFET DEVICES; THRESHOLD VOLTAGE;

FIELD EFFECT TRANSISTORS;

EID: 77952739506     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.49.054101     Document Type: Article

References (24)

1. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers: IEEE J. Solid-State Circuits 24 (1989) 1433.
2. K. J. Kuhn: IEDM Tech. Dig., 2007, p. 467.
3. T. Mizuno, J. Okamura, and A. Toriumi: IEEE Trans. Electron Devices 41 (1994) 2216.
4. A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva: IEEE Trans. Electron Devices 50 (2003) 1837.
5. A. Asenov: VLSI Tech. Dig., 2007, p. 86.
6. F. Tachibana and T. Hiramoto: Jpn. J. Appl. Phys. 44 (2005) 2147.
7. A. T. Putra, A. Nishida, S. Kamohara, and T. Hiramoto: Appl. Phys. Express 2 (2009) 024501.
8. A. T. Putra, A. Nishida, S. Kamohara, T. Tsunomura, and T. Hiramoto: Jpn. J. Appl. Phys. 48 (2009) 044502.
9. A. T. Putra, T. Tsunomura, A. Nishida, S. Kamohara, K. Takeuchi, and T. Hiramoto: Jpn. J. Appl. Phys. 48 (2009) 044502.
10. S. Ohkawa, M. Aoki, and H. Masuda: IEEE Trans. Semicond. Manuf. 17 (2004) 155.
11. M. Aoki, S. Ohkawa, and H. Masuda: Proc. 17th IEEE ICMTS, 2004, p. 201.
12. M. E. Mason: VLSI Tech. Dig., 2007, p. 90.
13. H. Onodera: VLSI Tech. Dig., 2007, p. 92.
14. K. Takeuchi, T. Fukai, T. Tsunomura, A. T. Putra, A. Nishida, S. Kamohara, and T. Hiramoto: IEDM Tech. Dig., 2007, p. 467.
15. T. Tsunomura, A. Nishida, F. Yano, A. T. Putra, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, and T. Mogami: VLSI Tech. Dig., 2008, p. 156.
16. T. Tsunomura, A. Nishida, and T. Hiramoto: IEEE Trans. Electron Devices 56 (2009) 2073.
17. T. Abo: VLSI Tech. Dig., 2007, p. 2.
18. S. Nassif, K. Bernstein, D. J. Frank, A. Gattiker, W. Haensch, B. L. Ji, E. Nowak, D. Pearson, and N. J. Rohrer: IEDM Tech. Dig., 2007, p. 569.
19. T. Tsunomura, A. Nishida, K. Takeuchi, S. Inaba, A. T. Putra, S. Kamohara, K. Terada, T. Hiramoto, and T. Mogami: Ext. Abstr. Solid State Devices and Materials, 2008, p. 860.
20. T. Tsunomura, A. Nishida, K. Takeuchi, S. Inaba, A. T. Putra, S. Kamohara, K. Terada, T. Hiramoto, and T. Mogami: Ext. Abstr. (56th Spring Meet., 2009); Japan Society of Applied Physics and Related Societies, 30p-V-15 [in Japanese].
21. K. Takeuchi: Silicon Nanoelectronics Workshop Abstr., 2007, p. 7.
22. T. Tsunomura, A. Nishida, and T. Hiramoto: Jpn. J. Appl. Phys. 48 (2009) 124505.
23. K. Takeuchi, T. Tatsumi, and A. Furukawa: IEDM Tech. Dig., 1997, p. 841.
24. N. Yasuda, H. Ota, T. Horikawa, T. Nabatame, H. Satake, A. Toriumi, Y. Tamura, T. Sasaki, and F. Ootsuka: Ext. Abstr. Solid State Devices and Materials, 2005, p. 250.