Modeling of electromigration in through-silicon-via based 3D IC

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 1420-1427

  Pak, Jiwoo ^a   Pathak, Mohit ^b   Lim, Sung Kyu ^b   Pan, David Z ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; CRITICAL PROBLEMS; DESIGN GUIDELINES; FEATURE SIZES; IC DESIGNS; IC TECHNOLOGY; INTERCONNECT RELIABILITY; METAL WIRES; RELATIVE POSITIONS; SYSTEMATIC STUDY; THERMO-MECHANICAL STRESS; THROUGH SILICON VIAS; THROUGH-SILICON-VIA;

ELECTROMIGRATION; ELECTRONICS PACKAGING; STRESSES; WIRE;

THREE DIMENSIONAL;

EID: 79960411499     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898698     Document Type: Conference Paper

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