Microstructure effect on EM-induced degradations in dual inlaid copper interconnects

IEEE Transactions on Device and Materials Reliability

Volumn 9, Issue 1, 2009, Pages 87-97

  Sukharev, Valeriy ^a   Kteyan, Armen ^a   Zschech, Ehrenfried ^b   Nix, William D ^c  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b AMD Fab 36 Limited Liability Company and Company KG   (Germany)

^c Stanford University   (United States)

Author keywords

Electromigration (EM); Simulation; Stress; Voiding

Indexed keywords

ATOMS; COPPER; DEGRADATION; ELECTROMIGRATION; ELECTRON DIFFRACTION; GRAIN BOUNDARIES; MICROSTRUCTURE; OPTICAL INTERCONNECTS; SCANNING ELECTRON MICROSCOPY;

ADDITIONAL STRESS; ATOM MIGRATIONS; ATOMIC TRANSPORTS; COPPER INTERCONNECT; COPPER INTERCONNECTS; COPPER LINES; COPPER MICROSTRUCTURES; CURRENT SIMULATIONS; DEGRADATION STUDIES; DEVELOPED MODELS; DUAL EFFECTS; ELECTRICAL DESIGNS; ELECTRON BACK-SCATTER DIFFRACTIONS; EXPERIMENTAL DATUM; FAILURE PROCESS; IN-SITU; INDUCED DEGRADATIONS; INDUCED STRESS; MICROSTRUCTURE ANALYSIS; MICROSTRUCTURE EFFECTS; MODULUS OF ELASTICITIES; NUMERICAL SIMULATIONS; PHYSICAL MODELS; SIMULATION; SIMULATION ALGORITHMS; SIMULATION RESULTS; STRESS EVOLUTIONS; VOID FORMATIONS; VOIDING;

COMPUTER SIMULATION;

EID: 61849180270     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2008.2011642     Document Type: Article

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