Electromigration performance of Through Silicon Via (TSV) - A modeling approach

Microelectronics Reliability

Volumn 50, Issue 9-11, 2010, Pages 1336-1340

  Tan, Y C ^a   Tan, C M ^a   Zhang, X W ^b   Chai, T C ^b   Yu, D Q ^b  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ASYMMETRIC BEHAVIORS; COVERAGE PATTERNS; DIFFERENT PROCESS; DOMINANT CONTRIBUTIONS; DYNAMIC SIMULATION; FINITE ELEMENT MODELING; METAL LINE; METALLIZATIONS; MODELING APPROACH; PROCESS TECHNOLOGIES; SIMULATION RESULT; THERMO-MECHANICAL STRESS; THROUGH-SILICON-VIA; VOID GROWTH;

ELECTROMIGRATION; METALLIZING; STRESSES;

COMPUTER SIMULATION;

EID: 79959316022     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2010.07.024     Document Type: Conference Paper

References (15)

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