Silicon nanowire tunneling field-effect transistor arrays: Improving subthreshold performance using excimer laser annealing

IEEE Transactions on Electron Devices

Volumn 58, Issue 7, 2011, Pages 1822-1829

  Smith, Joshua T ^a   Sandow, Christian ^b   Das, Saptarshi ^a   Minamisawa, Renato A ^b   Mantl, Siegfried ^b   Appenzeller, Joerg ^a  

^a PURDUE UNIVERSITY   (United States)

^b FORSCHUNGSZENTRUM JÜLICH   (Germany)

Author keywords

Excimer laser annealing (ELA); nanowire tunneling field effect transistor (NW TFET); steep slope transistors; ultrathin body silicon on insulator (SOI)

Indexed keywords

DOPING PROFILES; ELECTRICAL CHARACTERISTIC; EXCIMER LASER ANNEALING; EXPERIMENTAL DATA; LOW TEMPERATURES; OPTIMIZED DEVICES; PERFORMANCE PREDICTION; RAPID THERMAL ANNEAL; SI NANOWIRE; SILICON NANOWIRES; STEEP-SLOPE TRANSISTORS; SUBTHRESHOLD; SUBTHRESHOLD SLOPE; THEORETICAL LIMITS; TUNNELING FIELD-EFFECT TRANSISTORS; ULTRA-THIN-BODY;

ANNEALING; ELECTRIC WIRE; EXCIMER LASERS; FIELD EFFECT TRANSISTORS; NANOWIRES;

TRANSISTORS;

EID: 79959513719     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2135355     Document Type: Article

References (38)

1. J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris, "Band-to-band tunneling in carbon nanotube field-effect transistors," Phys. Rev. Lett., vol. 93, no. 19, pp. 196 805-1-196 805-4, Nov. 2004.
2. W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, "Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec," IEEE Electron Device Lett., vol. 28, no. 8, pp. 743-745, Aug. 2007. (Pubitemid 47243563)
3. T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, "Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and < 60 mV/dec subthreshold slope. in IEDM Tech. Dig. Dec. 2008; 1-3
4. M. Luisier and G. Klimeck, "Atomistic full-band design study of InAs band-to-band tunneling field-effect transistors," IEEE Electron Device Lett., vol. 30, no. 6, pp. 602-604, Jun. 2009.
5. M. Luisier and G. Klimeck, "Performance analysis of statistical samples of graphene nanoribbon tunneling transistors with line edge roughness," Appl. Phys. Lett., vol. 94, no. 22, pp. 223 505-1-223 505-3, Jun. 2009.
6. J. Knoch and J. Appenzeller, "Modeling of high-performance p-type III-V heterojunction tunnel FETs," IEEE Electron Device Lett., vol. 31, no. 4, pp. 305-307, Apr. 2010.
7. D. L. John, L. C. Castro, and D. L. Pulfrey, "Quantum capacitance in nanoscale device modeling," J. Appl. Phys., vol. 96, no. 9, pp. 5180-5184, Nov. 2004.
8. J. Knoch, W. Riess, and J. Appenzeller, "Outperforming the conventional scaling rules in the quantum-capacitance limit," IEEE Electron Device Lett., vol. 29, no. 4, pp. 372-374, Apr. 2008. (Pubitemid 351486785)
9. J. Appenzeller, J. Knoch, M. T. Björk, H. Riel, H. Schmid, and W. Riess, "Toward nanowire electronics," IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 2827-2845, Nov. 2008.
10. J. Knoch and J. Appenzeller, "Tunneling phenomena in carbon nanotube field-effect transistors," Phys. Stat. Sol. (A), vol. 205, no. 4, pp. 679-694, Apr. 2008.
11. M. T. Björk, J. Knoch, H. Schmid, H. Riel, and W. Riess, "Silicon nanowire tunneling field-effect transistors," Appl. Phys. Lett., vol. 92, no. 19, pp. 193 504-1-193 504-3, May 2008.
12. K. E. Moselund, H. Ghoneim, M. T. Björk, H. Schmid, S. Karg, E. Lörtscher, W. Riess, and H. Riel, "VLS-grown silicon nanowire tunnel FET," in Proc. 67th Device Res. Conf., Jun. 2009, pp. 23-24.
13. K. E. Moselund, H. Ghoneim, M. T. Björk, H. Schmid, S. Karg, E. Lörtscher, W. Riess, and H. Riel, "Comparison of VLS grown Si NW tunnel FETs with different gate stacks," in Proc. ESSDERC, Sep. 2009, pp. 448-451.
14. C. Sandow, C. Urban, Q.-T. Zhao, and S. Mantl, "Silicon and strained silicon nanowire array tunnel FETs," in Proc. ULIS Conf., Mar. 2010, pp. 109-112.
15. International Technology Roadmap for Semiconductors (ITRS). [Online]. Available: www.itrs.net
16. E. Koren, N. Berkovitch, and Y. Rosenwaks Measurement of active dopant distribution and diffusion in individual silicon nanowires Nano Lett. 10; 4: 1163-1167, Mar. 2010.
17. A. Florakis, N. Misra, C. Grigoropoulos, K. Giannakopoulos, A. Halimaoui, and D. Tsoukalas, "Non-melt laser annealing of plasma implanted boron for ultra shallow junctions in silicon," Mater. Sci. Eng. B. vol. 154/155, pp. 39-42, Dec. 2008.
18. S. Baek, S. Heo, H. Choi, and H. Hwang, "Characteristics of heavily doped p+/n ultrashallow junction prepared by plasma doping and laser annealing," J. Vac. Sci. Technol. B, Microelectron. Nanometer Struct., vol. 23, no. 1, pp. 257-261, Jan./Feb. 2005.
19. N. Misra, L. Xu, Y. L. Pan, N. Cheung, and C. P. Grigoropoulos, "Excimer laser annealing of silicon nanowires," Appl. Phys. Lett., vol. 90, no. 11, pp. 1111111-1111113, Mar. 2007.
20. G. Pepponi, D. Giubertoni, S. Gennaro, M. Bersani, A. Anderle, R. Grisenti, M. Werner, and J. A. Van Den Berg, "Local arsenic structure in shallow implant in Si following SPER: An EXAFS and MEIS study," in Proc. 16th Int. Conf. Ion Implantation Technol., vol. 866, AIP Conf. Proc., 2006, pp. 117-120.
21. D. Giubertoni, G. Pepponi, M. A. Sahiner, S. P. Kelty, S. Gennaro, M. Bersani, M. Kah, K. J. Kirby, R. Doherty, M. A. Foad, F. Meirer, C. Streli, J. C. Woicik, and P. Pianetta, "Deactivation of submelt laser annealed arsenic ultrashallow junctions in silicon during subsequent thermal treatment," J. Vac. Sci. Technol. B, Microelectron. Nanometer Struct., vol. 28, no. 1, pp. C1B1-C1B5, Mar. 2010.
22. S. Datta, Electronic Transport in Mesoscopic Systems. Cambridge, U.K.: Cambridge Univ. Press, 1997.
23. S. M. Sze, Physics of Semiconductor Devices, 3rd ed. Hoboken, NJ: Wiley, 2007.
24. J. Knoch, S. Mantl, and J. Appenzeller, "Impact of the dimensionality on the performance of tunneling FETs: Bulk versus one-dimensional devices," Solid State Electron., vol. 51, no. 4, pp. 572-578, Apr. 2007. (Pubitemid 46550579)
25. C. Sandow, J. Knoch, C. Urban, Q.-T. Zhao, and S. Mantl, "Impact of electrostatics and doping concentration on the performance of silicon tunnel field-effect transistors," Solid State Electron., vol. 53, no. 10, pp. 1126-1129, Oct. 2009.
26. R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, and M. Radosavljevic, "Benchmarking nan-otechnology for high-performance and low-power logic transistor applica-tions," IEEE Trans. Nanotechnol., vol. 4, no. 2, pp. 153-158, Mar. 2005. (Pubitemid 40421651)
27. T. Krishnamohan, D. Kim, C. D. Nguyen, C. Jungemann, Y. Nishi, and K. C. Saraswat, "High-mobility low band-to-band-tunneling strained-germanium double-gate heterostructure FETs: Simulations," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1000-1009, May 2006.
28. S. O. Koswatta, M. S. Lundstrom, and D. E. Nikonov, "Influence of phonon scattering on the performance of p-i-n band-to-band tunneling transistors," Appl. Phys. Lett., vol. 92, no. 4, pp. 043 125-1-043 125-3, Jan. 2008.
29. K. K. Dezfulian, J. P. Krusius, and M. O. Thompson, "Laser-induced lat-eral epitaxy in fully depleted silicon-on-insulator junctions," Appl. Phys. Lett., vol. 81, no. 12, pp. 2238-2240, Sep. 2002.
30. D. Giubertoni, G. Pepponi, M. Bersani, S. Gennaro, F. D'Acapito, R. Doherty, and M. A. Foad, "An EXAFS investigation of arsenic shallow implant activation in silicon after sub-melt annealing," Nucl. Instrum. Methods Phys. Res. B, Beam Interact. Mater. At., vol. 253, no. 1/2, pp. 9-12, Dec. 2006. (Pubitemid 44809470)
31. S. Severi, B. J. Pawlak, R. Duffy, E. Augendre, K. Henson, R. Lindsay, and K. De Meyer, "Arsenic junction thermal stability and high-dose boron-pocket activation during SPER in nMOS transistors," IEEE Electron De-vice Lett., vol. 28, no. 3, pp. 198-200, Mar. 2007.
32. P. M. Rousseau, P. B. Griffin, W. T. Fang, and J. D. Plummer, "Arsenic deactivation enhanced diffusion: A time, temperature, and concentration study," J. Appl. Phys., vol. 87, no. 7, pp. 3593-3601, Oct. 1998. (Pubitemid 128600492)
33. D. Nobili, S. Solmi, A. Parisini, M. Derdour, A. Armigliato, and L. Moro, "Precipitation, aggregation, and diffusion in heavily arsenic-doped silicon," Phys. Rev. B, Condens. Matter, vol. 49, no. 4, pp. 2477-2483, Jan. 1994.
34. D. Giubertoni, G. Pepponi, S. Gennaro, M. Bersani, M. A. Sahiner, S. P. Kelty, R. Doherty, M. A. Foad, M. Kah, K. J. Kirkby, J. C. Woicik, and P. Pianetta, "Correlation of local structure and electrical activation in arsenic ultrashallowjunctions in silicon," J. Appl. Phys., vol. 104, no. 10, pp. 103 716-1-103 716-8, Nov. 2008.
35. M. Orlowski, R. Subrahmanyan, and G. Huffman, "The effect of low-thermal-budget anneals and furnace ramps on the electrical activation of arsenic," J. Appl. Phys., vol. 71, no. 1, pp. 164-169, Jan. 1992.
36. N. D. Young, J. B. Clegg, and E. A. Maydell-Ondrusz, "Low- temperature annealing of shallow arsenic-implanted layers," J. Appl. Phys., vol. 61, no. 6, pp. 2189-2194, Mar. 1987.
37. D. D. D. Ma, C. S. Lee, F. C. K. Au, S. Y Tong, and S. T. Lee, "Small-diameter silicon nanowire surfaces," Science, vol. 299, no. 5614, pp. 1874-1877, Mar. 2003. (Pubitemid 36356653)
38. J. W. Sleight, S. Bangsaruntip, A. Majumdar, G. M. Cohen, Y Zhang, S. U. Engelmann, N. C. M. Fuller, L. M. Gignac, S. Mittal, J. S. New-bury, M. M. Frank, J. Chang, and M. Guillorn, "Gate-all-around sili-con nanowire MOSFETs and circuits," in Proc. 68th Device Res. Conf., Jun. 2010, pp. 269-272.