Comparison of VLS grown Si NW tunnel FETs with different gate stacks

ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference

Volumn , Issue , 2009, Pages 448-451

  Moselund, K E ^a   Ghoneim, H ^a   Bjork M T ^a   Schmid, H ^a   Karg, S ^a   Lortscher E ^a   Riess, W ^a   Riel, H ^a  

^a IBM RESEARCH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

GATE STACKS; HIGH-K GATE DIELECTRICS; HIGH-K GATE STACKS; LOW TEMPERATURES; ON-CURRENTS; SILICON NANOWIRES; TUNNEL FET; TUNNELING FIELD-EFFECT TRANSISTORS;

ELECTRIC WIRE; GATE DIELECTRICS; GATES (TRANSISTOR); LOGIC GATES; SILICON COMPOUNDS; SILICON OXIDES; WIND TUNNELS;

FIELD EFFECT TRANSISTORS;

EID: 72849132345     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2009.5331446     Document Type: Conference Paper

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