A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates

Solid-State Electronics

Volumn 62, Issue 1, 2011, Pages 31-39

  Lu, Darsen D ^a   Dunga, Mohan V ^a   Lin, Chung Hsun ^a   Niknejad, Ali M ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Berkeley short channel insulated gate FET model (BSIM); Compact modeling; Computational efficiency; Double gate MOSFET; Fully depleted SOI MOSFET

Indexed keywords

APPROXIMATION SCHEME; BACK-GATE; CHARGE MODELS; CHARGE-SHEET APPROXIMATION; COMPACT MODEL; COMPACT MODELING; COMPUTATIONAL TIME; COMPUTATIONALLY EFFICIENT; CONVERGENCE DIFFICULTY; DOUBLE-GATE DEVICE; DOUBLE-GATE MOSFET; EXPLICIT ANALYTICAL EQUATION; FULL MODEL; FULLY DEPLETED; INSULATED GATE; NONIDEAL EFFECTS; NUMERICAL ITERATION; RING OSCILLATOR CIRCUITS; SOI-MOSFETS; SOURCE-DRAIN; SURFACE-POTENTIAL-BASED MODELS; TCAD SIMULATION; TRANSIENT SIMULATION; VERILOG-A; VOLUME INVERSION;

COMPUTATIONAL EFFICIENCY; COMPUTER SIMULATION; DRAIN CURRENT; MOSFET DEVICES; OSCILLATORS (ELECTRONIC); SURFACE POTENTIAL; SURFACE PROPERTIES;

SILICON ON INSULATOR TECHNOLOGY;

EID: 79957942166     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2010.12.015     Document Type: Article

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