A closed-form charge-based expression for drain current in symmetric and asymmetric double gate MOSFET

Solid-State Electronics

Volumn 50, Issue 4, 2006, Pages 687-693

  Roy, A S ^a   Sallese, J M ^a   Enz, C C ^a,b  

^a EPFL   (Switzerland)

^b CSEM   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; GATES (TRANSISTOR); MATHEMATICAL MODELS; NUMERICAL ANALYSIS; SOLID STATE DEVICES; TRANSCONDUCTANCE;

DG MOST; DRAIN CURRENTS; SOLID-STATE ELECTRONS; TRANSCONDUCTANCE-TO-CURRENT RATIO;

MOSFET DEVICES;

EID: 33646535276     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2006.03.021     Document Type: Article

References (6)

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3. Balestra F., Cristoloveanu S., Benachir M., Brini J., and Elewa T. Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance. IEEE Electron Dev Lett 8 (1987) 410
4. Kim K., and Fossum J.G. Double-gate CMOS: symmetrical- versus asymmetrical-gate devices. IEEE Trans Electron Dev 48 2 (2001) 294-299
5. Taur Y. Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFET. IEEE Trans Electron Dev 48 12 (2001) 2861-2869
6. Sylveira M., Flandre D., and Gespers P.A. A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA. IEEE J Solid-State Circ 31 9 (1996) 1314-1319