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Volumn 1, Issue , 1997, Pages 343-346
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Modeling the threshold voltage of long and short-channel fully depleted SOI MOSFETs with back gate substrate induced surface effects
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER SIMULATION;
GATES (TRANSISTOR);
LAPLACE TRANSFORMS;
SEMICONDUCTING SILICON;
SEMICONDUCTOR DEVICE MODELS;
SEMICONDUCTOR DEVICE STRUCTURES;
SEMICONDUCTOR JUNCTIONS;
SILICON ON INSULATOR TECHNOLOGY;
POISSON'S EQUATION;
SOFTWARE PACKAGE PISCES;
SUBSTRATE INDUCED SURFACE POTENTIALS (SISP);
MOSFET DEVICES;
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EID: 0031369121
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (2)
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References (7)
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