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Volumn , Issue , 2011, Pages 236-245

A HW/SW co-designed heterogeneous multi-core virtual machine for energy-efficient general purpose computing

Author keywords

Binary Optimization; Energy Efficiency; Heterogeneous multi cores; HW SW Co designed Virtual Machine; Single Thread Performance

Indexed keywords

BINARY OPTIMIZATION; ENERGY EFFICIENT; EXPERIMENT AND ANALYSIS; GENERAL PURPOSE; GENERAL PURPOSE PROCESSORS; GENERAL-PURPOSE COMPUTING; HETEROGENEOUS MULTICORE; HW/SW CO-DESIGNED VIRTUAL MACHINE; MARKET SEGMENT; MULTI-CORES; OUT OF ORDER; POWER EFFICIENT; SINGLE-THREAD PERFORMANCE; SPECIAL PURPOSE PROCESSORS; VIRTUAL MACHINES;

EID: 79957513404     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CGO.2011.5764691     Document Type: Conference Paper
Times cited : (11)

References (36)
  • 1
    • 77958453327 scopus 로고    scopus 로고
    • Power Management Enhancements in the 45nm Intel Core™ Microarchitecture
    • Oct
    • J. Allarey, V. George, S. Jahagirdar, "Power Management Enhancements in the 45nm Intel Core™ Microarchitecture," Intel Tech Journal, Vol. 12, Issue 3, Oct 2008.
    • (2008) Intel Tech Journal , vol.12 , Issue.3
    • Allarey, J.1    George, V.2    Jahagirdar, S.3
  • 3
    • 34547473118 scopus 로고    scopus 로고
    • Computation Spreading: Employing Hardware Migration to Specialize CMP Cores On-the-fly
    • K. Chakraborty P. M. Wells, G. S. Sohi, "Computation Spreading: Employing Hardware Migration to Specialize CMP Cores On-the-fly," ASPLOS'2006
    • ASPLOS'2006
    • Chakraborty, K.1    Wells, P.M.2    Sohi, G.S.3
  • 6
    • 84943385246 scopus 로고    scopus 로고
    • The Transmeta Code Morphing Software: Using Speculation, Recovery, and Adaptive Retranslation to Address Real-Life Challenges
    • Dehnert, J. C, Grant, B., Banning, J. P., Johnson, R., Kistler, T, Klaiber, A., and Mattson, J. "The Transmeta Code Morphing Software: Using Speculation, Recovery, and Adaptive Retranslation to Address Real-Life Challenges". CGO'2003.
    • CGO'2003
    • Dehnert, J.C.1    Grant, B.2    Banning, J.P.3    Johnson, R.4    Kistler, T.5    Klaiber, A.6    Mattson, J.7
  • 7
    • 84944415710 scopus 로고    scopus 로고
    • Comparing Program Phase Detection Techniques
    • Dhodapkar, A. and J. Smith, "Comparing Program Phase Detection Techniques", Micro-36, 2003.
    • (2003) Micro-36
    • Dhodapkar, A.1    Smith, J.2
  • 8
    • 0030645966 scopus 로고    scopus 로고
    • Daisy: Dynamic Compilation for 100% Architectural Compatibility
    • Ebcioglu, K.; Altman, E.R.; "Daisy: Dynamic Compilation For 100% Architectural Compatibility", ISCA-24, 1997
    • (1997) ISCA-24
    • Ebcioglu, K.1    Altman, E.R.2
  • 9
    • 84944745122 scopus 로고    scopus 로고
    • Performance and power impact of issue-width in chip-multiprocessor cores
    • Ekman, M, P. Stenstrom, "Performance and power impact of issue-width in chip-multiprocessor cores," ICPP 2003.
    • ICPP 2003
    • Ekman, M.1    Stenstrom, P.2
  • 10
    • 64849117951 scopus 로고    scopus 로고
    • Bridging the Computation Gap between Programmable Processors and Hardwired Accelerators
    • Feb.
    • Fan, K., M. Kudlur, G. Dasika, and S. Mahlke, "Bridging the Computation Gap Between Programmable Processors and Hardwired Accelerators", HPCA-15, Feb. 2009, pp. 313-322.
    • (2009) HPCA-15 , pp. 313-322
    • Fan, K.1    Kudlur, M.2    Dasika, G.3    Mahlke, S.4
  • 11
    • 35448978700 scopus 로고    scopus 로고
    • Energy per Instruction Trends in Intel Microprocessors
    • March
    • Grochowski, E. and M. Annavaram, "Energy per Instruction Trends in Intel Microprocessors", Technology@ Intel Magazine, March 2006, pp 1-8.
    • (2006) Technology@ Intel Magazine , pp. 1-8
    • Grochowski, E.1    Annavaram, M.2
  • 12
    • 33749377408 scopus 로고    scopus 로고
    • Stream programming on general-purpose processors
    • Gummaraju, J., Rosenblum, M.; "Stream programming on general-purpose processors," MICRO-38. 2005.
    • (2005) MICRO-38
    • Gummaraju, J.1    Rosenblum, M.2
  • 13
    • 67650093493 scopus 로고    scopus 로고
    • Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors
    • July
    • Homayoun, H., S. Pasricha , M. Makhzan, A. Veidenbaum, "Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors," ACM SIGPLAN Notices, v.43 n.7, July 2008
    • (2008) ACM SIGPLAN Notices , vol.43 , Issue.7
    • Homayoun, H.1    Pasricha, S.2    Makhzan, M.3    Veidenbaum, A.4
  • 15
    • 33845905757 scopus 로고    scopus 로고
    • Reducing startup time in co-designed virtual machines
    • DOI 10.1109/ISCA.2006.33, 1635959, Proceedings - 33rd International Symposium on Computer Architecture,ISCA 2006
    • Hu, S., and J. E. Smith, "Reducing Startup Time in Co-Designed Virtual Machines." ISCA 2006: 277-288 (Pubitemid 46016622)
    • (2006) Proceedings - International Symposium on Computer Architecture , vol.2006 , pp. 277-288
    • Hu, S.1    Smith, J.E.2
  • 16
    • 77954753229 scopus 로고    scopus 로고
    • Software Data Spreading: Leveraging Distributed Caches to Improve Single Thread Performance
    • Kamruzzaman, M. S. Swanson, D. M. Tullsen, "Software Data Spreading: Leveraging Distributed Caches to Improve Single Thread Performance", PLDI 2010
    • PLDI 2010
    • Kamruzzaman1    Swanson, M.S.2    Tullsen, D.M.3
  • 18
    • 84944384783 scopus 로고    scopus 로고
    • Hardware Support for Control Transfers in Code Caches
    • Kim, H., J. E. Smith, "Hardware Support for Control Transfers in Code Caches." MICRO 2003: 253-264
    • MICRO 2003 , pp. 253-264
    • Kim, H.1    Smith, J.E.2
  • 21
    • 34247174509 scopus 로고    scopus 로고
    • Core architecture optimization for heterogeneous chip multiprocessors
    • Kumar, R, D.Tullsen, N.Jouppi, "Core architecture optimization for heterogeneous chip multiprocessors", PACT-15, 2006
    • (2006) PACT-15
    • Kumar, R.1    Tullsen, D.2    Jouppi, N.3
  • 22
    • 2942729643 scopus 로고    scopus 로고
    • Design and Implementation of a Lightweight Dynamic Optimization System
    • Lu, J., H. Chen, P. Yew, W. Hsu, "Design and Implementation of a Lightweight Dynamic Optimization System". J. Instruction- Level Parallelism 6: (2004)
    • (2004) J. Instruction- Level Parallelism , vol.6
    • Lu, J.1    Chen, H.2    Yew, P.3    Hsu, W.4
  • 23
    • 0038633609 scopus 로고    scopus 로고
    • Itanium 2 processor microarchitecture
    • March
    • McNairy, C.; Soltis, D.; "Itanium 2 processor microarchitecture, " IEEE Micro, Volume: 23 , Issue: 2. (March 2003)
    • (2003) IEEE Micro , vol.23 , Issue.2
    • McNairy, C.1    Soltis, D.2
  • 24
    • 77952255139 scopus 로고    scopus 로고
    • A real system evaluation of hardware atomicity for software speculation
    • Neelakantam, N., Ditzel, D., and Zilles, C. "A real system evaluation of hardware atomicity for software speculation." ASPLOS-15, 2010
    • (2010) ASPLOS-15
    • Neelakantam, N.1    Ditzel, D.2    Zilles, C.3
  • 26
    • 0035363244 scopus 로고    scopus 로고
    • rePLay: A hardware framework for dynamic optimization
    • DOI 10.1109/12.931895
    • Patel, S.J., Lumetta, S.S., "rePLay: A hardware framework for dynamic optimization," IEEE Transactions on Computers, Jun 2001, Vol: 50 Issue:6, PP: 590-608 (Pubitemid 32609869)
    • (2001) IEEE Transactions on Computers , vol.50 , Issue.6 , pp. 590-608
    • Patel, S.J.1    Lumetta, S.S.2
  • 28
    • 79957527954 scopus 로고    scopus 로고
    • NVIDIA GeForce 200M GPU Update - Power numbers and efficiency
    • Jun 18
    • Shrout, R., "NVIDIA GeForce 200M GPU Update - Power numbers and efficiency", PC Perspective, Jun 18, 2009.
    • (2009) PC Perspective
    • Shrout, R.1
  • 33
    • 67650033098 scopus 로고    scopus 로고
    • Accelerating critical section execution with asymmetric multi-core architectures
    • M. A. Suleman, O. Mutlu, M. K. Qureshi, Y. N. Patt, "Accelerating critical section execution with asymmetric multi-core architectures". ASPLOS 2009.
    • ASPLOS 2009
    • Suleman, M.A.1    Mutlu, O.2    Qureshi, M.K.3    Patt, Y.N.4
  • 34
    • 70449711370 scopus 로고    scopus 로고
    • Dynamic parallelization of single-threaded binary programs using speculative slicing
    • Wang, C., Y. Wu, E. Borin, S. Hu, W. Liu, D. Sager, T. Ngai, J. Fang, "Dynamic parallelization of single-threaded binary programs using speculative slicing". ICS 2009, pp. 158-168
    • ICS 2009 , pp. 158-168
    • Wang, C.1    Wu, Y.2    Borin, E.3    Hu, S.4    Liu, W.5    Sager, D.6    Ngai, T.7    Fang, J.8
  • 35
    • 3042653317 scopus 로고    scopus 로고
    • The Accuracy of Initial Prediction in Two-Phase Dynamic Binary Translators
    • Wu, Y., M. Breternitz Jr., J. Quek, O. Etzion, J. Fang: "The Accuracy of Initial Prediction in Two-Phase Dynamic Binary Translators." CGO 2004. PP 227-238
    • CGO 2004 , pp. 227-238
    • Wu, Y.1    Breternitz Jr., M.2    Quek, J.3    Etzion, O.4    Fang, J.5
  • 36
    • 77954986440 scopus 로고    scopus 로고
    • Energy-Performance Tradeoffs in Processor Architecture and Circuit Design: A Marginal Cost Analysis
    • Azizi, O., A. Mahesri, B. Lee, S. Patel, M. Horowitz, "Energy-Performance Tradeoffs in Processor Architecture and Circuit Design: A Marginal Cost Analysis", ISCA 2010
    • ISCA 2010
    • Azizi, O.1    Mahesri, A.2    Lee, B.3    Patel, S.4    Horowitz, M.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.