-
1
-
-
3042560116
-
Specialized Dynamic Optimizations for High-Performance Energy-Efficient Mi-croarchitecture
-
to appear
-
Y. Almog, R. Rosner, N. Schwartz and A. Schmorak, "Specialized Dynamic Optimizations for High-Performance Energy-Efficient Mi- croarchitecture", to appear in CGO'04.
-
CGO'04
-
-
Almog, Y.1
Rosner, R.2
Schwartz, N.3
Schmorak, A.4
-
2
-
-
0004092514
-
Transparent Dynamic Optimization: The Design and Implementation of Dynamo
-
HP Labs
-
V. Bala, E. Duesterwald and S. Banerjia, "Transparent Dynamic Optimization: The Design and Implementation of Dynamo", TR HPL-1999-78, HP Labs.
-
TR HPL-1999-78
-
-
Bala, V.1
Duesterwald, E.2
Banerjia, S.3
-
3
-
-
0029728522
-
Performance and Hardware Complexity Tradeoffs in Designing Multithreaded Architectures
-
Oct.
-
M. Bekerman, A. Mendelson and G Shcaffer, "Performance and Hardware Complexity Tradeoffs in Designing Multithreaded Architectures", in PACT, pp 24-34, Oct. 1996.
-
(1996)
PACT
, pp. 24-34
-
-
Bekerman, M.1
Mendelson, A.2
Shcaffer, G.3
-
4
-
-
3042688073
-
Turboscalar: A High Frequency High IPC Microarchitecture
-
June
-
B. Black and J.P. Shen, "Turboscalar: A High Frequency High IPC Microarchitecture", in ISCA27, June 2000.
-
(2000)
ISCA27
-
-
Black, B.1
Shen, J.P.2
-
5
-
-
0034316092
-
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors
-
Nov./Dec.
-
D.M. Brooks et al, "Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors", IEEE Micro, 20(6):36-44, Nov./Dec. 2000.
-
(2000)
IEEE Micro
, vol.20
, Issue.6
, pp. 36-44
-
-
Brooks, D.M.1
-
6
-
-
3042692388
-
Thermal-Scheduling for Ultra Low Power Mobile Microprocessor
-
G. Cai, C.H. Lim and W.R. Daasch, "Thermal-Scheduling For Ultra Low Power Mobile Microprocessor", in. WCED'02, 2002.
-
(2002)
WCED'02
-
-
Cai, G.1
Lim, C.H.2
Daasch, W.R.3
-
7
-
-
0030645966
-
DAISY: Dynamic Compilation for 100% Architectural Compatibility
-
K. Ebcioglu and E.R. Altman, "DAISY: Dynamic Compilation for 100% Architectural Compatibility", in ISCA24, pp. 26-37, 1997.
-
(1997)
ISCA24
, pp. 26-37
-
-
Ebcioglu, K.1
Altman, E.R.2
-
8
-
-
0035694429
-
Permormance Characterization of a Hardware Mechanism for Dynamic Optimization
-
B. Fahs, S. Bose, M. Crum, B. Slechta, F. Spadini, T. Tung, S.J. Patel and S.S. Lumetta, "Permormance Characterization of a Hardware Mechanism for Dynamic Optimization", MICRO34, 2001.
-
(2001)
MICRO34
-
-
Fahs, B.1
Bose, S.2
Crum, M.3
Slechta, B.4
Spadini, F.5
Tung, T.6
Patel, S.J.7
Lumetta, S.S.8
-
9
-
-
1142270696
-
Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors
-
Nov.
-
D. Friendly, S. Patel and Y. Patt, "Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors", in MICRO31, Nov. 1998.
-
(1998)
MICRO31
-
-
Friendly, D.1
Patel, S.2
Patt, Y.3
-
10
-
-
0033889996
-
Dynamic and Transparent Binary Translation
-
M. Gschwind, E.R. Altman, S. Sathaye, P. Ledak and D. Appenzeller, "Dynamic and Transparent Binary Translation", in IEEE Computer Magazine 33(3), pp. 54-59, 2000.
-
(2000)
IEEE Computer Magazine
, vol.33
, Issue.3
, pp. 54-59
-
-
Gschwind, M.1
Altman, E.R.2
Sathaye, S.3
Ledak, P.4
Appenzeller, D.5
-
11
-
-
0003278283
-
The Microarchitecture of the Pentium® 4 Processor
-
G. Hinton, D. Sager, M. Upton, D. Boggs, D. Carmean, A. Kyker and P. Roussel, "The Microarchitecture of the Pentium® 4 Processor", in Intel Technology Journal, 2001.
-
(2001)
Intel Technology Journal
-
-
Hinton, G.1
Sager, D.2
Upton, M.3
Boggs, D.4
Carmean, D.5
Kyker, A.6
Roussel, P.7
-
13
-
-
0033308141
-
Extended Block Cache
-
Jan.
-
S. Jourdan, L. Rappoport, Y. Almog, M. Erez, A. Yoaz, and R. Ronen, "extended Block Cache", in HPCA6, Jan. 2000.
-
(2000)
HPCA6
-
-
Jourdan, S.1
Rappoport, L.2
Almog, Y.3
Erez, M.4
Yoaz, A.5
Ronen, R.6
-
15
-
-
0026867146
-
Limits of Control Flow on Parallelism
-
May
-
M.S. Lam and R.P. Wilson, "Limits of Control Flow on Parallelism", in Proc. 19th ISCA, pp. 46-57, May 1992.
-
(1992)
Proc. 19th ISCA
, pp. 46-57
-
-
Lam, M.S.1
Wilson, R.P.2
-
16
-
-
0002745357
-
Effective Compiler Support for Predicated Execution using the Hyperblock
-
S.A. Mahlke, D.C. Lin, W.Y. Chen, R.E. Hank and R.A. Bringmann, "Effective Compiler Support for Predicated Execution using the Hyperblock", in MICRO25, 1992.
-
(1992)
MICRO25
-
-
Mahlke, S.A.1
Lin, D.C.2
Chen, W.Y.3
Hank, R.E.4
Bringmann, R.A.5
-
17
-
-
0029326787
-
Enhancing Instruction Scheduling with a Block-Structured ISA
-
Jun.
-
S. Melvin and Y Patt, "Enhancing Instruction Scheduling with a Block-Structured ISA", in Intern. Journal of Parallel Prog., 23(3) pp 221-243, Jun. 1995
-
(1995)
Intern. Journal of Parallel Prog.
, vol.23
, Issue.3
, pp. 221-243
-
-
Melvin, S.1
Patt, Y.2
-
18
-
-
0032629113
-
A Hardware-Driven Profiling Scheme for Identifying Program Hot Spots to Support Runtime Optimization
-
M.C. Merten, A.R. Trick, C.N. George, J. Gyllenhaal, and W.W. Hwu, "A Hardware-Driven Profiling Scheme for Identifying Program Hot Spots to Support Runtime Optimization", ISCA26, 1999.
-
(1999)
ISCA26
-
-
Merten, M.C.1
Trick, A.R.2
George, C.N.3
Gyllenhaal, J.4
Hwu, W.W.5
-
19
-
-
0033700757
-
A Hardware Mechanism for Dynamic Extraction and Relayout of Program Hot Spots
-
May
-
M.C. Merten, A.R. Trick, E. M. Nystrom, R.D. Barnes and W. Mwu, "A Hardware Mechanism for Dynamic Extraction and Relayout of Program Hot Spots", in ISCA27, May 2000.
-
(2000)
ISCA27
-
-
Merten, M.C.1
Trick, A.R.2
Nystrom, E.M.3
Barnes, R.D.4
Mwu, W.5
-
20
-
-
0030674213
-
Exploiting instruction level parallelism in processors by caching scheduled groups
-
R. Nair. and M.E. Hopkins, "Exploiting instruction level parallelism in processors by caching scheduled groups", in Proc. ISCA24, pp. 13-25, 1997.
-
(1997)
Proc. ISCA24
, pp. 13-25
-
-
Nair, R.1
Hopkins, M.E.2
-
22
-
-
0035363244
-
RePlay: A Hardware Framework for Dynamic Optimization
-
June
-
S. Patel and S. Lumetta, "rePlay: A Hardware Framework for Dynamic Optimization", in IEEE Trans, on Computers, 50(6), pp 590-608, June 2001
-
(2001)
IEEE Trans, on Computers
, vol.50
, Issue.6
, pp. 590-608
-
-
Patel, S.1
Lumetta, S.2
-
23
-
-
0034461965
-
Increasing the Size of Atomic Instruction Blocks using Control Flow Assertions
-
S. Patel, T. Tung, S Bose and M. Crum, "Increasing the Size of Atomic Instruction Blocks using Control Flow Assertions", in MICRO33, 2000.
-
(2000)
MICRO33
-
-
Patel, S.1
Tung, T.2
Bose, S.3
Crum, M.4
-
24
-
-
35048845868
-
-
"Dynamic Flow Instruction Cache Memory Organized Around Trace Segments Independent of Virtual Address Line", U.S. Patent 5,381,533, Jan.
-
A. Peleg and U. Weiser, "Dynamic Flow Instruction Cache Memory Organized Around Trace Segments Independent of Virtual Address Line", U.S. Patent 5,381,533, Jan. 1995.
-
(1995)
-
-
Peleg, A.1
Weiser, U.2
-
26
-
-
0035186012
-
Filtering Techniques to Improve Trace-Cache Efficiency
-
Sept.
-
R. Rosner, A. Mendelson and R. Ronen, "Filtering Techniques to Improve Trace-Cache Efficiency", in PACT'01, Sept. 2001.
-
(2001)
PACT'01
-
-
Rosner, R.1
Mendelson, A.2
Ronen, R.3
-
27
-
-
1142305201
-
Selecting Long Atomic Traces for High Coverage
-
R. Rosner, M. Moffie, Y. Sazeides and R. Ronen, "Selecting Long Atomic Traces for High Coverage", in ICS'03, pp. 2-11, 2003.
-
(2003)
ICS'03
, pp. 2-11
-
-
Rosner, R.1
Moffie, M.2
Sazeides, Y.3
Ronen, R.4
-
28
-
-
0033077095
-
A trace cache microarchitecture and evaluation
-
Feb.
-
E. Rotenberg, S. Bennett and J. Smith, "A trace cache microarchitecture and evaluation", in IEEE Trans, on Computers, 48(2), pp 111-120, Feb. 1999
-
(1999)
IEEE Trans, on Computers
, vol.48
, Issue.2
, pp. 111-120
-
-
Rotenberg, E.1
Bennett, S.2
Smith, J.3
-
29
-
-
0034863487
-
Micro-Operation Cache: A Power Aware Frontend for Variable Instruction Length ISA
-
Aug.
-
B. Solomon, R. Ronen, D. Orenstien, Y. Almog and A. Mendelson "Micro-Operation Cache: A Power Aware Frontend for Variable Instruction Length ISA", in ISLPED'01, Aug. 2001.
-
(2001)
ISLPED'01
-
-
Solomon, B.1
Ronen, R.2
Orenstien, D.3
Almog, Y.4
Mendelson, A.5
-
30
-
-
1142270675
-
Dynamic Optimizations of Micro-Operations
-
Feb.
-
B. Slechta et al, "Dynamic Optimizations of Micro-Operations", in HPCA9, Feb. 2003.
-
(2003)
HPCA9
-
-
Slechta, B.1
-
31
-
-
84948974161
-
Optimizing Pipelines for Power and Performance
-
V. Srinivasan, D. Brooks, M. Gschwind, P. Bose, V. Zyuban, P.N. Strenski and P.G. Emma, "Optimizing Pipelines for Power and Performance", in MICRO 35, 2002.
-
(2002)
MICRO
, vol.35
-
-
Srinivasan, V.1
Brooks, D.2
Gschwind, M.3
Bose, P.4
Zyuban, V.5
Strenski, P.N.6
Emma, P.G.7
|