Itanium 2 processor microarchitecture

IEEE Micro

Volumn 23, Issue 2, 2003, Pages 44-55

  McNairy, Cameron ^b   Soltis, Don ^a  

^a HEWLETT PACKARD COMPANY   (United States)

^b MS 55 ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER OPERATING SYSTEMS; DATA STORAGE EQUIPMENT; PROGRAM COMPILERS;

BINARY COMPATIBILITY;

MICROPROCESSOR CHIPS;

EID: 0038633609     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2003.1196114     Document Type: Article

References (7)

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2. J. Huck et al., "Introducing the IA-64 Architecture" IEEE Micro, vol. 20, no. 5, Sept.-Oct. 2000, pp. 12-23.
3. D. Bradley, P. Mahoney, and B. Stackhouse, "The 16KB Single-Cycle Read Access Cache on a Next Generation 64b Itanium Microprocessor," Proc. 2002 IEEE Int'l Solid-State Circuits Conf. (ISSCC 02), IEEE Press, 2002, pp. 110-111.
4. T.-Y. Yeh and Y.N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction," Proc. 19th Int'l Symp. Computer Architecture (ISCA 92), ACM Press, 1992, pp. 124-134.
5. T. Lyon et al., "Data Cache Design Considerations for the Itanium 2 Processor," Proc. 2002 IEEE Int'l Conf. Computer Design: VLSI In Computers and Processors (ICCD 02), IEEE Press, 2002, pp. 356-362.
6. J. McCormick and A. Knies, "A Brief Analysis of the SPEC CPU2000 Benchmarks on the Intel Itanium 2 Processor," 2002; http://www.hotchips.org/archive/index.html.
7. E.S. Fetzer and J.T. Orton, "A Fully-Bypassed 6-Issue Integer Datapath and Register File on an Itanium Microprocessor," Proc. 2002 IEEE Int'l Sold-State Circuits Conf. (ISSCC 02), IEEE Press, 2002, pp. 420-478.