Performance and power impact of issue-width in chip-multiprocessor cores

Proceedings of the International Conference on Parallel Processing

Volumn 2003-January, Issue , 2003, Pages 359-368

  Ekman, M ^a   Stenstrom, P ^a  

^a CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

Concurrent computing; Energy consumption; Out of order; Parallel processing; Performance loss; Pipelines; Power engineering and energy; Power engineering computing; Protocols; System on a chip

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED ENGINEERING; ECONOMIC AND SOCIAL EFFECTS; ELECTRIC POWER UTILIZATION; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NETWORK PROTOCOLS; PIPELINES; SYSTEM-ON-CHIP;

CONCURRENT COMPUTING; OUT OF ORDER; PARALLEL PROCESSING; PERFORMANCE LOSS; POWER ENGINEERING AND ENERGIES; POWER ENGINEERING COMPUTING; SYSTEM ON A CHIP;

PIPELINE PROCESSING SYSTEMS;

EID: 84944745122     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2003.1240600     Document Type: Conference Paper

References (26)

1. R. I. Bahar, S. Manne: Power and energy reduction via pipeline balancing. International Symposium on Computer Architecture, 2001, 218-229
2. L. Barosso, K. Gharachorloo, R. McNamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, B. Verghese. Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing. In Proc. of International Symposium on Computer Architecture, pages 282-293, 2000.
3. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. In Proc. of International Symposium on Computer Architecture. pages 83-94, June, 2000.
4. M. Ekman, F. Dahlgren and P. Stenstrom. TLB and Snoop Energy-Reduction using Virtual Caches in Low-Power Chip Multiprocessors, In Proceedings of International Symposium on Low Power Electronics and Design, August 2002.
5. D. Burger and T. Austin. The SimpleScalar Tool Set Ver. 2.0. University of Wisconsin-Madison, Computer Sciences Department, Technical Report #1342, 1997.
6. J. Chen, M. Dubois, and P. Stenstrom: SimWattch: An Approach to Integrate Complete-System with User-Level Performance/Power Simulators. In Proc of IEEE ISPASS-2003, March 2003.
7. R. Gonzales and M. Horowitz. Energy Dissipation In General Purpose Microprocessors. IEEE Journal of Solid-State Circuits, pages 1277-1284, September 1996.
8. K. Flautner, N. Kim, S. Martin, D. Blaauw, T. Mudge. Drowsy Caches: Simple Techniques for Reducing Leakage Power. International Symposium on Computer Architecture, 2002.
9. D. Folegnani and A. Gonzales. Energy-Effective Issue Logic. In Proc. of International Symposium on Computer Architecture, 2001, pages 230-239.
10. L. Hammond, B. Hubbert, M. Siu, M. Prabhu, M. Chen, K. Olukotun. The Stanford Hydra. In IEEE Micro, pages 71-84, 2000.
11. J. Huh, S. W. Keckler and D. Burger. Exploring the Design Space of Future CMPs. In Proc. of International Conference on Parallel Architectures and Compilation Techniques, 2001.
12. S. Kaxiras, Z. Hu and M. Martonosi: Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power. In Proc. of International Symposium on Computer Architecture, 2001, pages 240-251.
13. J. Lo, L. Barosso, S. Eggers, K. Gharachorloo, H. Levy, and S. Parekh. An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors. In 25th Annual International Symposium on Computer Architecture, pages 94-105, 1998.
14. P. S. Magnusson, F. Dahlgren, H. Grahn, M. Karlsson, F. Larsson. F. Lundholm, A. Moestedt, J. Nilsson, P. Stenstrom and B. Werner. SimICS/sun4m: A Virtual Workstation. In Proc. Usenix Annual Technical Conference, Jun. 1998, pp. 119-130.
15. C. Mauer, M. Hill, and D. Wood. Full System Timing-First Simulation. In Proc. of SIGMETRICS, June 2002.
16. T. Mudge. Power: A first class design constraint. In Computer, vol. 34, no. 4, pages 52-57, April 2001.
17. K. Olukotun, B. Nayfeh, L. Hammond, K. Wilson, and K.-Y. Chang. The Case for a Single-Chip Multiprocessor. In Proc. of 7th International Conference on Architectural Support for Programming Languages and Operating Systems. 1996.
18. K. Olukotun, L. Hammond, and M. Willey. Improving the Performance of Speculatively Parallel Applications on the HYDRA CMP. In Proc. of the 1999 Int. Conf on Supercomputing, pages 21-30, June 1999.
19. S. Palacharla, N. Jouppi, and J.-E. Smith. Complexity-Effective Superscalar Processors. In 24th Ann. International Symposium on Computer Architecture. pp. 206-218, 1997.
20. P. Ranganathan, K. Gharachorloo, S. Adve, and L. Barosso. Performance of Database Workloads on Shared-memory Systems with Out-of-Order Processors. In Proc. of 8th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 307-318, Oct. 1998.
21. J. Steffan, C. Colohan, A. Zhai, and T. Mowry. The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization. In Proc. of the 8th Int. Symp. on High-Performance Computer Architecture, pages 2-13. Feb 2002.
22. J. M. Tendler, J. S. Dodson, J. S. Fields Jr, H. Le and B. Sinharoy. POWER4 System Microarchitecture. IBM Journal of Research and Development, Vol. 46 No. 1, January 2002.
23. M. Tremblay, J. Chen, S. Chaudry, A. Conigliaro, and S-S Tse. The MAJC Architecture: A Synthesis of Parallelism and Scalability. In IEEE Micro, pages 12-25, 2000.
24. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh and A. Gupta. The SPLASH-2 programs: Characterization and methodological considerations. In Proc. of the 22th International Symposium on Computer Architecture, pages 24-36, June 1995.
25. V. Zyuban and P. Kogge. Optimization of High-Performance Superscalar Architectures for Energy Efficiency. In Proc. of International Symposium on Low Power Electronics and Design, August 2000.
26. V. Zyuban and P. Kogge. Inherently Lower-Power High-Performance Superscalar Architectures. IEEE Transactions on Computers, Volume: 50, Issue: 3, March 2001.