-
5
-
-
0032662989
-
Simultaneous subordinate microthreading (ssmt)
-
R. Chappell, J. Stark, S. Kim, S. Reinhardt, and Y. Patt. Simultaneous subordinate microthreading (ssmt). In Proceedings of the international symposium on Computer Architecture, May 1999.
-
Proceedings of the International Symposium on Computer Architecture, May 1999
-
-
Chappell, R.1
Stark, J.2
Kim, S.3
Reinhardt, S.4
Patt, Y.5
-
7
-
-
0034839033
-
Speculative precomputation: Long-range prefetching of delinquent loads
-
J. Collins, H. Wang, D. Tullsen, C. Hughes, Y.-F. Lee, D. Lavery, and J. Shen. Speculative precomputation: Long-range prefetching of delinquent loads. In Proceedings of the International Symposium on Computer Architecture, July 2001.
-
Proceedings of the International Symposium on Computer Architecture, July 2001
-
-
Collins, J.1
Wang, H.2
Tullsen, D.3
Hughes, C.4
Lee, Y.-F.5
Lavery, D.6
Shen, J.7
-
8
-
-
0034226001
-
SPEC CPU2000: Measuring cpu performance in the new millennium
-
July
-
J. L. Henning. SPEC CPU2000: Measuring cpu performance in the new millennium. Computer, July 2000.
-
(2000)
Computer
-
-
Henning, J.L.1
-
10
-
-
32844471317
-
A NUCA substrate for flexible CMP cache sharing
-
J. Huh, C. Kim, H. Shafi, L. Zhang, D. Burger, and S. Keckler. A NUCA substrate for flexible CMP cache sharing. In International Conference on Supercomputing, June 2005.
-
International Conference on Supercomputing, June 2005
-
-
Huh, J.1
Kim, C.2
Shafi, H.3
Zhang, L.4
Burger, D.5
Keckler, S.6
-
13
-
-
3042569221
-
Physical experiment with prefetching helper threads on Intel's hyper-threaded processors
-
D. Kim, S. Liao, P. Wang, J. Cuvillo, X. Tian, X. Zou, H. Wang, D. Yeung, M. Girkar, and J. Shen. Physical experiment with prefetching helper threads on Intel's hyper-threaded processors. In International Symposium on Code Generation and Optimization, March 2004.
-
International Symposium on Code Generation and Optimization, March 2004
-
-
Kim, D.1
Liao, S.2
Wang, P.3
Cuvillo, J.4
Tian, X.5
Zou, X.6
Wang, H.7
Yeung, D.8
Girkar, M.9
Shen, J.10
-
15
-
-
57749178620
-
System level analysis of fast, per-core dvfs using on-chip switching regulators
-
W. Kim, M. S. Gupta, G.-Y. Wei, and D. Brooks. System level analysis of fast, per-core dvfs using on-chip switching regulators. Proceedings of the 14th International Symposium on High Performance Computer Architecture, February 2008.
-
Proceedings of the 14th International Symposium on High Performance Computer Architecture, February 2008
-
-
Kim, W.1
Gupta, M.S.2
Wei, G.-Y.3
Brooks, D.4
-
17
-
-
0033348795
-
A chip-multiprocessor architecture with speculative multithreading
-
September
-
V. Krishnan and J. Torrellas. A chip-multiprocessor architecture with speculative multithreading". IEEE Transactions on Computers, September 1999.
-
(1999)
IEEE Transactions on Computers
-
-
Krishnan, V.1
Torrellas, J.2
-
19
-
-
4644370318
-
Single-isa heterogeneous multi-core architectures for multithreaded workload performance
-
R. Kumar, D. M. Tullsen, P. Ranganathan, N. P. Jouppi, and K. I. Farkas. Single-isa heterogeneous multi-core architectures for multithreaded workload performance. In Proceedings of the 31st Annual International Symposium on Computer Architecture, June 2004.
-
Proceedings of the 31st Annual International Symposium on Computer Architecture, June 2004
-
-
Kumar, R.1
Tullsen, D.M.2
Ranganathan, P.3
Jouppi, N.P.4
Farkas, K.I.5
-
21
-
-
0036036248
-
Postpass binary adaptation for software-based speculative precomputation
-
S. Liao, P. Wang, H. Wang, G. Hoflehner, D. Lavery, and J. Shen. Postpass binary adaptation for software-based speculative precomputation. In Proceedings of the conference on Programming Language Design and Implementation, October 2002.
-
Proceedings of the Conference on Programming Language Design and Implementation, October 2002
-
-
Liao, S.1
Wang, P.2
Wang, H.3
Hoflehner, G.4
Lavery, D.5
Shen, J.6
-
24
-
-
31944440969
-
Pin: Building customized program analysis tools with dynamic instrumentation
-
C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. Pin: building customized program analysis tools with dynamic instrumentation. In Proceedings of the 2005 conference on Programming Language Design and Implementation, June 2005.
-
Proceedings of the 2005 Conference on Programming Language Design and Implementation, June 2005
-
-
Luk, C.-K.1
Cohn, R.2
Muth, R.3
Patil, H.4
Klauser, A.5
Lowney, G.6
Wallace, S.7
Reddi, V.J.8
Hazelwood, K.9
-
27
-
-
61749104310
-
Niagara 2 opens the floodgates
-
November
-
H. McGhan. Niagara 2 opens the floodgates. Microprocessor Reports, November 2006.
-
(2006)
Microprocessor Reports
-
-
McGhan, H.1
-
28
-
-
0003660453
-
The organization of matrices and matrix operations in a paged multiprogramming environment
-
Mar.
-
A. McKeller and E. Coffman. The organization of matrices and matrix operations in a paged multiprogramming environment. Communications of the ACM, Mar. 1969.
-
(1969)
Communications of the ACM
-
-
McKeller, A.1
Coffman, E.2
-
30
-
-
31844447800
-
Mitosis compiler: An infrastructure for speculative threading based on pre-computation slices
-
C. G. Quiñones, C. Madriles, J. Sánchez, P. Marcuello, A. González, and D. M. Tullsen. Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices. In ACM SIGPLAN Conference on Programming Language Design and Implementation, June 2005.
-
ACM SIGPLAN Conference on Programming Language Design and Implementation, June 2005
-
-
Quiñones, C.G.1
Madriles, C.2
Sánchez, J.3
Marcuello, P.4
González, A.5
Tullsen, D.M.6
-
32
-
-
77952284721
-
Fast switching of threads between cores
-
April
-
R. Strong, J. Mudigonda, J. C. Mogul, N. Binkert, and D. Tullsen. Fast switching of threads between cores. SIGOPS Oper. Syst. Rev., April 2009.
-
(2009)
SIGOPS Oper. Syst. Rev.
-
-
Strong, R.1
Mudigonda, J.2
Mogul, J.C.3
Binkert, N.4
Tullsen, D.5
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