Data marshaling for multi-core architectures

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2010, Pages 441-450

  Suleman, M Aater ^a   Mutlu, Onur ^b   Joao, José A ^a   Khubaib, ^a   Patt, Yale N ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

CMP; Critical sections; Pipelining; Staged execution

Indexed keywords

CACHE MISS; CMP; CRITICAL SECTIONS; EXECUTION MODEL; HETEROGENEOUS MULTICORE; MULTICORE ARCHITECTURES; PERFORMANCE BENEFITS; STORAGE OVERHEAD;

COMPUTER CONTROL SYSTEMS; COMPUTERS; MICROPROCESSOR CHIPS;

COMPUTER ARCHITECTURE;

EID: 77954973999     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1815961.1816020     Document Type: Conference Paper

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