A real system evaluation of hardware atomicity for software speculation

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2010, Pages 29-38

  Neelakantam, Naveen ^a,b   Ditzel, David R ^b   Zilles, Craig ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Atomicity; Checkpoint; Dynamic translation; Optimization; Speculation

Indexed keywords

ATOMIC REGIONS; ATOMICITY; COMMERCIAL PRODUCTS; COMMERCIAL SYSTEMS; DYNAMIC TRANSLATION; LINE CODES; NEGATIVE SIDE EFFECTS; OPTIMIZERS; PERFORMANCE DYNAMICS; PERFORMANCE IMPROVEMENTS; PERFORMANCE PENALTIES; REAL SYSTEMS; SIDE EFFECT; SOFTWARE COMPLEXITY; SOFTWARE CONTROL; SOURCE CODES; STATIC CODES; TRANSLATION SYSTEMS;

COMPUTER OPERATING SYSTEMS; COMPUTER SOFTWARE SELECTION AND EVALUATION; LINGUISTICS; OPTIMIZATION; TRANSLATION (LANGUAGES);

ATOMS;

EID: 77952255139     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1736020.1736026     Document Type: Conference Paper

References (20)

1. V. Bala, E. Duesterwald, and S. Banerjia. Dynamo: A Transparent Dynamic Optimization System. In Proceedings of the SIGPLAN 2000 Conference on Programming Language Design and Implementation, pages 1-12, 2000.
2. C. Blundell, M. M. Martin, and T. F. Wenisch. Invisifence: performance-transparent memory ordering in conventional multiprocessors. In Proceedings of the 36th International Symposium on Computer Architecture, pages 233-244, 2009.
3. R. A. Bringmann, S. A. Mahlke, R. E. Hank, J. C. Gyllenhaal, and W.-m.W. Hwu. Speculative execution exception recovery using write-back suppression. In Proceedings of the 26th International Symposium on Microarchitecture, pages 214-223, 1993.
4. B. Cmelik and D. Keppel. Shade: A fast instruction-set simulator for execution profiling. ACM SIGMETRICS Performance Evaluation Review, 22(1):128-137, May 1994.
5. J. C. Dehnert et al. The Transmeta Code Morphing Software: Using Speculation, Recovery, and Adaptive Retranslation to Address Real-life Challenges. In Proceedings of the International Symposium on Code Generation and Optimization, pages 15-24, 2003.
6. J. A. Fisher. Trace scheduling: a technique for global microcode compaction. IEEE Transactions on Computers, 30(7):478-490, 1981.
7. S. Gochman, R. Ronen, I. Anati, A. Berkovits, T. Kurts, A. Naveh, A. Saeed, Z. Sperber, and R. C. Valentine. The Intel® Pentium® M Processor: Microarchitecture and Performance. Intel Technology Journal, 7(2):21-36, 2003.
8. S. Gopal, T. Vijaykumar, J. Smith, and G. Sohi. Speculative versioning cache. In Proceedings of the 4th International Symposium on High-Performance Computer Architecture, page 195, 1998.
9. W. M. Hwu et al. The Superblock: An Effective Technique for VLIW and Superscalar Compilation. Journal of Supercomputing, 7(1):229-248, Mar 1993.
10. A. Klaiber. The Technology Behind Crusoe Processors. Transmeta Whitepaper, Jan. 2000.
11. J. R. Larus and R. Rajwar. Transactional Memory. Morgan and Claypool, Dec. 2006.
12. S. A. Mahlke, W. Y. Chen, R. A. Bringmann, R. E. Hank, W.-M. W. Hwu, B. R. Rau, and M. S. Schlansker. Sentinel scheduling: a model for compiler-controlled speculative execution. ACM Trans. Comput. Syst., 11(4):376-408, 1993.
13. S. A. Mahlke, D. C. Lin, W. Y. Chen, R. E. Hank, and R. A. Bringmann. Effective compiler support for predicated execution using the hyperblock. In In Proceedings of the 25th International Symposium on Microarchitecture, pages 45-54, 1992.
14. N. Neelakantam, R. Rajwar, S. Srinivas, U. Srinivasan, and C. Zilles. Hardware atomicity for reliable software speculation. In Proceedings of the 34th International Symposium on Computer Architecture, pages 174-185, 2007.
15. S. J. Patel and S. S. Lumetta. rePLay: A Hardware Framework for Dynamic Optimization. IEEE Transactions on Computers, 50(6):590-608, 2001.
16. R. Rajwar and J. R. Goodman. Speculative lock elision: Enabling highly concurrent multithreaded execution. In Proceedings of the 34th International Symposium on Microarchitecture, pages 294-305, 2001.
17. G. Rozas. Memory management methods and systems that support cache consistency. United States Patent 7,376,798, May 2008.
18. G. Rozas, A. Klaiber, D. Dunn, P. Serris, and L. Shah. Supporting speculative modification in a data cache. United States Patent 7,225,299, May 2007.
19. M. D. Smith, M. Horowitz, and M. S. Lam. Efficient superscalar performance through boosting. In Proceedings of the 5th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 248-259, 1992.
20. C. Zilles and N. Neelakantam. Reactive Techniques for Controlling Software Speculation. In Proceedings of the International Symposium on Code Generation and Optimization, pages 305-316, 2005.