Bridging the computation gap between programmable processors and hardwired accelerators

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2009, Pages 313-322

  Fan, Kevin ^a,b   Kudlury, Manjunath ^a,c   Dasika, Ganesh ^a   Mahlke, Scott ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b Parakinetics

^c NVIDIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATION; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER HARDWARE; EFFICIENCY; GENERAL PURPOSE COMPUTERS; REUSABILITY; SIGNAL PROCESSING;

CUSTOMIZED SOLUTIONS; GENERAL PURPOSE PROCESSORS; HARDWARE IMPLEMENTATIONS; LOOP ACCELERATORS; POWER CONSTRAINTS; POWER EFFICIENCY; PROGRAMMABLE PROCESSORS; SIGNAL PROCESSING APPLICATIONS;

COMPUTER ARCHITECTURE;

EID: 64849117951     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2009.4798266     Document Type: Conference Paper

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