Energy-performance tradeoffs in processor architecture and circuit design: A marginal cost analysis

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2010, Pages 26-36

  Azizi, Omid ^a   Mahesri, Aqeel ^b   Lee, Benjamin C ^a   Patel, Sanjay J ^c   Horowitz, Mark ^a  

^a Stanford University   (United States)

^b NVIDIA   (United States)

^c University of Illinois at Urbana Champaign   (United States)

Author keywords

Co optimization; Design space exploration; Design trade offs; Energy efficiency; Microarchitecture; Optimization

Indexed keywords

CIRCUIT DESIGNS; CIRCUIT OPTIMIZATION; CO-OPTIMIZATION; DESIGN OBJECTIVES; DESIGN SPACE EXPLORATION; DESIGN TRADEOFF; INTEGRATED ARCHITECTURE; JOINT ARCHITECTURES; LARGE PARTS; MARGINAL COSTS; MICRO ARCHITECTURES; OPTIMAL ARCHITECTURE; OPTIMAL ENERGY; OUT OF ORDER; PERFORMANCE TRADE-OFF; POWER CONSUMPTION; PROCESSOR ARCHITECTURES; PROCESSOR DESIGN; VOLTAGE-SCALING;

CAPACITANCE; COMMERCE; COMPUTERS; COST ACCOUNTING; COST BENEFIT ANALYSIS; DESIGN; ENERGY EFFICIENCY; INTEGRATED CIRCUIT MANUFACTURE; NANOTECHNOLOGY; OPTIMIZATION; SPACE RESEARCH;

COMPUTER ARCHITECTURE;

EID: 77954986440     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1815961.1815967     Document Type: Conference Paper

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