SCOPUS 정보 검색 플랫폼

Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference

Volumn , Issue , 2005, Pages 199-202

A 2GHz 13.6mW 12×9b multiplier for energy efficient FFT accelerators

(8) Hsu, Steven a Venkatraman, Vishak a Mathew, Sanu a Kaul, Himanshu a Anders, Mark a Dighe, Saurabh a Burleson, Wayne a Krishnamurthy, Ram a

a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRON MULTIPLIERS; ENERGY EFFICIENCY; FAST FOURIER TRANSFORMS; FLIP FLOP CIRCUITS; SIGNAL PROCESSING; TREES (MATHEMATICS);

LEAKAGE POWER; NOISE TOLERANCE; TREE ARCHITECTURE; TWIDDLE MULTIPLIERS;

ELECTROSTATIC ACCELERATORS;

EID: 33749189194 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ESSCIR.2005.1541594 Document Type: Conference Paper

Times cited : (9)

References (7)

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6
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7
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- Design Compiler. Synthesis and Power Estimation Toolset

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